.. |
.gitignore
|
3010cc7892
Permissions Changes
|
16 jaren geleden |
INPUT_A.txt
|
733954ace9
Change the remaining circuits from microsecond to nanoscale time scale,
|
16 jaren geleden |
INPUT_B.txt
|
733954ace9
Change the remaining circuits from microsecond to nanoscale time scale,
|
16 jaren geleden |
alu-fast.asc
|
8bf16f88b2
The behavioral ALU model, alu-fast, now works.
|
16 jaren geleden |
alu-fast.asy
|
d14abb6cf0
Add alu-fast, a behavorial model of a comparing ALU. Not working.
|
16 jaren geleden |
alu-fast_test.asc
|
a0643e4f62
Partially fix alu, by slowing down the transitions.
|
16 jaren geleden |
alu-fast_test.plt
|
8bf16f88b2
The behavioral ALU model, alu-fast, now works.
|
16 jaren geleden |
alu.asc
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05c7b1ee58
Improve names of components in main.asc and alu.asc.
|
16 jaren geleden |
alu.asy
|
400a66a116
Fix the ALU and properly test it (including difference, not just sign output).
|
16 jaren geleden |
alu_test.asc
|
400a66a116
Fix the ALU and properly test it (including difference, not just sign output).
|
16 jaren geleden |
alu_test.plt
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400a66a116
Fix the ALU and properly test it (including difference, not just sign output).
|
16 jaren geleden |
clock_gen-fast.asc
|
6c1cb50931
Update comments about clock gen.
|
16 jaren geleden |
clock_gen-fast.asy
|
3f171c1e01
Move the inverter out of the clock generator (both versions) and into main.
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16 jaren geleden |
clock_gen-fast_test.asc
|
7eaa408938
Rename clock_gen with PULSE voltage source to clock_gen-fast, since it is.
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16 jaren geleden |
clock_gen-fast_test.plt
|
7eaa408938
Rename clock_gen with PULSE voltage source to clock_gen-fast, since it is.
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16 jaren geleden |
clock_gen.asc
|
6c1cb50931
Update comments about clock gen.
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16 jaren geleden |
clock_gen.asy
|
3f171c1e01
Move the inverter out of the clock generator (both versions) and into main.
|
16 jaren geleden |
clock_gen_test.asc
|
d46c59be12
Shorten simulation time by 5/2 for clock_gen_test.
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16 jaren geleden |
clock_gen_test.plt
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588d5f2c54
Fix clock_gen_test.asc file.
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16 jaren geleden |
control_parts.asc
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31b02a7555
Correctly name the 1:3 decoder (was incorrectly named as a 3:1 decoder).
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16 jaren geleden |
cycle_up_instance.asc
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22d54879f8
Add instances of cycle_up, decoder, inverter, and min used for logic board creation.
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16 jaren geleden |
decoder1-3.asc
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873fda810b
Add notes about more efficient implementations of 1:3 decoder and 9:3 mux.
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16 jaren geleden |
decoder1-3.asy
|
31b02a7555
Correctly name the 1:3 decoder (was incorrectly named as a 3:1 decoder).
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16 jaren geleden |
decoder1-3_test.asc
|
31b02a7555
Correctly name the 1:3 decoder (was incorrectly named as a 3:1 decoder).
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16 jaren geleden |
decoder1-3_test.plt
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31b02a7555
Correctly name the 1:3 decoder (was incorrectly named as a 3:1 decoder).
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16 jaren geleden |
decoder_instance.asc
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22d54879f8
Add instances of cycle_up, decoder, inverter, and min used for logic board creation.
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16 jaren geleden |
diode_test.asc
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dc2be664ad
Add symbols, subcircuits, and a test circuit for FD and RD Gates.
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16 jaren geleden |
diode_test.plt
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2f6225f905
Save plot settings for FD and RD gates.
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16 jaren geleden |
dtflop-et.asc
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53434f58d9
In the latches and flip-flop, use diagonal wires for the cross-coupled
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16 jaren geleden |
dtflop-et.asy
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4b5888b176
Add an attempt at an edge-triggered D flip-flop, using an inverter and
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16 jaren geleden |
dtflop-et_test.asc
|
4b5888b176
Add an attempt at an edge-triggered D flip-flop, using an inverter and
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16 jaren geleden |
dtflop-et_test.plt
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4b5888b176
Add an attempt at an edge-triggered D flip-flop, using an inverter and
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16 jaren geleden |
dtflop-ms2.asc
|
71b63dac86
Label all nodes meaningfully as possible.
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16 jaren geleden |
dtflop-ms2.asy
|
998662b26f
Rename dtflop-et-ms to dtflop-ms2, everywhere.
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16 jaren geleden |
dtflop-ms2_test.asc
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650c5bfbb8
Export dtflop-ms2_test to SPICE netlist, with better node names.
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16 jaren geleden |
dtflop-ms2_test.plt
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998662b26f
Rename dtflop-et-ms to dtflop-ms2, everywhere.
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16 jaren geleden |
dtflop-msmo.asc
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07d9594910
Rename dtflop-ms to dtflop-msmo (for Mouftah), since it has drawbacks.
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16 jaren geleden |
dtflop-msmo.asy
|
07d9594910
Rename dtflop-ms to dtflop-msmo (for Mouftah), since it has drawbacks.
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16 jaren geleden |
dtflop-msmo_test.asc
|
ad1756634f
In dtflop-msmo_test, show how dtflop-msmo and dtflop-ms2 differ.
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16 jaren geleden |
dtflop-msmo_test.plt
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ad1756634f
In dtflop-msmo_test, show how dtflop-msmo and dtflop-ms2 differ.
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16 jaren geleden |
dtflop.asc
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71b63dac86
Label all nodes meaningfully as possible.
|
16 jaren geleden |
dtflop.asy
|
bb70144d49
Center all <InstName> attributes on the symbols.
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16 jaren geleden |
dtflop2.asc
|
70fba43cc3
Add synchronous inputs to dtflop2, an experimental D-type tri-flop
|
16 jaren geleden |
dtflop2.asy
|
70fba43cc3
Add synchronous inputs to dtflop2, an experimental D-type tri-flop
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16 jaren geleden |
dtflop2_test.asc
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70fba43cc3
Add synchronous inputs to dtflop2, an experimental D-type tri-flop
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16 jaren geleden |
dtflop2_test.plt
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45a448c109
Add an experimental D-type flip-flop with asynchronous inputs. Not tested.
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16 jaren geleden |
dtflop_test.asc
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92f42f8e74
Add a power supply to the D-type flip-flop test circuit, and change it to
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16 jaren geleden |
dtflop_test.plt
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92f42f8e74
Add a power supply to the D-type flip-flop test circuit, and change it to
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16 jaren geleden |
dtlatch.asc
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71b63dac86
Label all nodes meaningfully as possible.
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16 jaren geleden |
dtlatch.asy
|
bb70144d49
Center all <InstName> attributes on the symbols.
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16 jaren geleden |
dtlatch_test.asc
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28ef9619ca
Add a ring oscillator, built with 17 simple ternary inverters, that
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16 jaren geleden |
dtlatch_test.plt
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46ff8bc067
Add saved plot settings for dtflop and dtlatch, so that after simulating,
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16 jaren geleden |
fd.asc
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597752acff
Restore FD and RD to D model again since it works, update 1/2 + & - plot settings.
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16 jaren geleden |
fd.asy
|
dc2be664ad
Add symbols, subcircuits, and a test circuit for FD and RD Gates.
|
16 jaren geleden |
full_adder.asc
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31b02a7555
Correctly name the 1:3 decoder (was incorrectly named as a 3:1 decoder).
|
16 jaren geleden |
full_adder.asy
|
971558aaf5
Add a full-adder, based on the design by Srivastava and Venkatapathy
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16 jaren geleden |
full_adder_test.asc
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557cc77e90
Name *-test.* to *_test.*, for consistency.
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16 jaren geleden |
full_adder_test.plt
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557cc77e90
Name *-test.* to *_test.*, for consistency.
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16 jaren geleden |
half_adder.asc
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0971f08b1e
Use the fd and rd subcircuits in the half-adder, breaking it.
|
16 jaren geleden |
half_adder.asy
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012e129f7f
Rename adder to half_adder.
|
16 jaren geleden |
half_adder_test.asc
|
012e129f7f
Rename adder to half_adder.
|
16 jaren geleden |
half_adder_test.plt
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597752acff
Restore FD and RD to D model again since it works, update 1/2 + & - plot settings.
|
16 jaren geleden |
half_subtractor.asc
|
3ab16959f2
Add a half-working half-subtractor.
|
16 jaren geleden |
half_subtractor.asy
|
3ab16959f2
Add a half-working half-subtractor.
|
16 jaren geleden |
half_subtractor_test.asc
|
3ab16959f2
Add a half-working half-subtractor.
|
16 jaren geleden |
half_subtractor_test.plt
|
597752acff
Restore FD and RD to D model again since it works, update 1/2 + & - plot settings.
|
16 jaren geleden |
input_n.txt
|
733954ace9
Change the remaining circuits from microsecond to nanoscale time scale,
|
16 jaren geleden |
input_p.txt
|
733954ace9
Change the remaining circuits from microsecond to nanoscale time scale,
|
16 jaren geleden |
input_z.txt
|
733954ace9
Change the remaining circuits from microsecond to nanoscale time scale,
|
16 jaren geleden |
inverter_instance.asc
|
22d54879f8
Add instances of cycle_up, decoder, inverter, and min used for logic board creation.
|
16 jaren geleden |
logic_board.asc
|
d616e5a932
Logic board: add 4 buffers (need 3 for ALU), and remove 3 tinv's to save space.
|
16 jaren geleden |
main.asc
|
3f171c1e01
Move the inverter out of the clock generator (both versions) and into main.
|
16 jaren geleden |
main.plt
|
3f171c1e01
Move the inverter out of the clock generator (both versions) and into main.
|
16 jaren geleden |
main_cmptest.asc
|
74ee971842
Add main architecture with cmptest instruction.
|
16 jaren geleden |
main_cmptest.plt
|
74ee971842
Add main architecture with cmptest instruction.
|
16 jaren geleden |
main_jmptest.asc
|
376ea0d90d
Split main to main-jmptest, and add swrom-jmptest.
|
16 jaren geleden |
main_jmptest.plt
|
376ea0d90d
Split main to main-jmptest, and add swrom-jmptest.
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16 jaren geleden |
main_lwitest.asc
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ea1ae44eb0
TCA0 (main_lwitest): replace with latest TCA2 architecture, but without BE and CMP.
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16 jaren geleden |
main_lwitest.plt
|
ea1ae44eb0
TCA0 (main_lwitest): replace with latest TCA2 architecture, but without BE and CMP.
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16 jaren geleden |
max.asc
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71b63dac86
Label all nodes meaningfully as possible.
|
16 jaren geleden |
max.asy
|
516ea2a9b9
Add "3" to symbol dyadic gates, so it is clearer that they are trinary.
|
16 jaren geleden |
min.asc
|
71b63dac86
Label all nodes meaningfully as possible.
|
16 jaren geleden |
min.asy
|
516ea2a9b9
Add "3" to symbol dyadic gates, so it is clearer that they are trinary.
|
16 jaren geleden |
min_instance.asc
|
22d54879f8
Add instances of cycle_up, decoder, inverter, and min used for logic board creation.
|
16 jaren geleden |
mux3-1.asc
|
31b02a7555
Correctly name the 1:3 decoder (was incorrectly named as a 3:1 decoder).
|
16 jaren geleden |
mux3-1.asy
|
ef789bccc2
In the 3:1 mux, move the S input within the symbol.
|
16 jaren geleden |
mux3-1_test.asc
|
b0a37135fd
Changed name of power supplies in mux3-1_test.asc
|
16 jaren geleden |
mux3-1_test.plt
|
a925a08992
Save plot settings for 3:1 mux.
|
16 jaren geleden |
mux9-3.asc
|
873fda810b
Add notes about more efficient implementations of 1:3 decoder and 9:3 mux.
|
16 jaren geleden |
mux9-3.asy
|
06feb8e046
Add swrom (untested).
|
16 jaren geleden |
nti.asc
|
6947b90592
Improve reference designator names for dtflop-ms and
|
16 jaren geleden |
nti.asy
|
bb70144d49
Center all <InstName> attributes on the symbols.
|
16 jaren geleden |
pti.asc
|
6947b90592
Improve reference designator names for dtflop-ms and
|
16 jaren geleden |
pti.asy
|
bb70144d49
Center all <InstName> attributes on the symbols.
|
16 jaren geleden |
pznflop.asc
|
71b63dac86
Label all nodes meaningfully as possible.
|
16 jaren geleden |
pznflop.asy
|
7895ecef8d
PZN tri-flop, untested (second try).
|
16 jaren geleden |
pznflop_test.asc
|
057f8ef746
Demonstrate that pznflop (clocked) functions correctly, now that tnand3 is fixed.
|
16 jaren geleden |
pznflop_test.plt
|
057f8ef746
Demonstrate that pznflop (clocked) functions correctly, now that tnand3 is fixed.
|
16 jaren geleden |
pznlatch.asc
|
53434f58d9
In the latches and flip-flop, use diagonal wires for the cross-coupled
|
16 jaren geleden |
pznlatch.asy
|
61fe926297
Add clocked PZN flip-flop, untested.
|
16 jaren geleden |
pznlatch_test.asc
|
f03b5e831a
Rename pznflop to pznlatch, because one common convention now dictates that
|
16 jaren geleden |
pznlatch_test.plt
|
f03b5e831a
Rename pznflop to pznlatch, because one common convention now dictates that
|
16 jaren geleden |
rd.asc
|
597752acff
Restore FD and RD to D model again since it works, update 1/2 + & - plot settings.
|
16 jaren geleden |
rd.asy
|
dc2be664ad
Add symbols, subcircuits, and a test circuit for FD and RD Gates.
|
16 jaren geleden |
ring_oscillator.asc
|
093a58aeba
Remove a spurious net label.
|
16 jaren geleden |
ring_oscillator.plt
|
6e6a66c88b
Make a ring oscillator with a TNAND gate to initialize it. Original
|
16 jaren geleden |
ring_oscillator_with_ic.asc
|
6e6a66c88b
Make a ring oscillator with a TNAND gate to initialize it. Original
|
16 jaren geleden |
shift_down.asc
|
989124e47e
Add shift down gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates.
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16 jaren geleden |
shift_down.asy
|
989124e47e
Add shift down gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates.
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16 jaren geleden |
shift_test.asc
|
989124e47e
Add shift down gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates.
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16 jaren geleden |
shift_test.plt
|
989124e47e
Add shift down gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates.
|
16 jaren geleden |
shift_up.asc
|
989124e47e
Add shift down gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates.
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16 jaren geleden |
shift_up.asy
|
d80e93413b
Add a shift up gate built using Mouftah's gates (untested).
|
16 jaren geleden |
sp3t-1.asc
|
d002756e2c
Make trit-X files for i,0,1; which look like switches set to either i, 0, or 1.
|
16 jaren geleden |
sp3t-1.asy
|
f41deba04b
Reorder SP3T models pin tables to match the NKK SS14M SP3T switches.
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16 jaren geleden |
sp3t-2.asc
|
695ef87e1c
Fix sp3t-2, so that trit_test correctly simulates and finds the operating points.
|
16 jaren geleden |
sp3t-2.asy
|
f41deba04b
Reorder SP3T models pin tables to match the NKK SS14M SP3T switches.
|
16 jaren geleden |
sp3t-3.asc
|
d002756e2c
Make trit-X files for i,0,1; which look like switches set to either i, 0, or 1.
|
16 jaren geleden |
sp3t-3.asy
|
f41deba04b
Reorder SP3T models pin tables to match the NKK SS14M SP3T switches.
|
16 jaren geleden |
sp3t_test.asc
|
d002756e2c
Make trit-X files for i,0,1; which look like switches set to either i, 0, or 1.
|
16 jaren geleden |
sti.asc
|
71b63dac86
Label all nodes meaningfully as possible.
|
16 jaren geleden |
sti.asy
|
bb70144d49
Center all <InstName> attributes on the symbols.
|
16 jaren geleden |
swrom-blank.asc
|
707e1376d2
Replace sp3t with trit-0 in swrom-blank. New models.
|
16 jaren geleden |
swrom-cmptest.asc
|
47ba6e4f70
Add cmptest, to test the CMP instruction.
|
16 jaren geleden |
swrom-cmptest.asy
|
47ba6e4f70
Add cmptest, to test the CMP instruction.
|
16 jaren geleden |
swrom-fast.asc
|
6079843376
Change swrom-fast symbol to use i, 0, and 1 instead of 0, 1, 2,
|
16 jaren geleden |
swrom-fast.asy
|
e4b28cbfee
Add symbol and test for behavorial model of 3x3 SWROM with guess.t loaded.
|
16 jaren geleden |
swrom-fast_test.asc
|
ffe64e5f80
Change swrom-fast to accept a program given on the top-level
|
16 jaren geleden |
swrom-fast_test.plt
|
e4b28cbfee
Add symbol and test for behavorial model of 3x3 SWROM with guess.t loaded.
|
16 jaren geleden |
swrom-guess.asc
|
4acda26f9c
Add swrom loaded with guess.t.
|
16 jaren geleden |
swrom-guess.asy
|
4acda26f9c
Add swrom loaded with guess.t.
|
16 jaren geleden |
swrom-jmptest.asc
|
376ea0d90d
Split main to main-jmptest, and add swrom-jmptest.
|
16 jaren geleden |
swrom-jmptest.asy
|
376ea0d90d
Split main to main-jmptest, and add swrom-jmptest.
|
16 jaren geleden |
swrom-lwitest.asc
|
12af1d5bce
Add swrom-lwitest, a switch-ROM with lwitest.3 loaded, and
|
16 jaren geleden |
swrom-lwitest.asy
|
12af1d5bce
Add swrom-lwitest, a switch-ROM with lwitest.3 loaded, and
|
16 jaren geleden |
swrom.asc
|
376ea0d90d
Split main to main-jmptest, and add swrom-jmptest.
|
16 jaren geleden |
swrom.asy
|
9fc48c519a
Change switch-ROM bits (from asm/guess.t assembled) to use $G_Vss and $G_Vdd,
|
16 jaren geleden |
swrom_test.asc
|
9fc48c519a
Change switch-ROM bits (from asm/guess.t assembled) to use $G_Vss and $G_Vdd,
|
16 jaren geleden |
swrom_test.plt
|
78486c24b1
Clean up: remove Draft2 circuit, add v(address) to swrom_test.plt.
|
16 jaren geleden |
tbuf.asc
|
1c0cd268e8
Add a new tbuf subcircuit, two simple ternary inverters.
|
16 jaren geleden |
tbuf.asy
|
1c0cd268e8
Add a new tbuf subcircuit, two simple ternary inverters.
|
16 jaren geleden |
tcycle_down.asc
|
71b63dac86
Label all nodes meaningfully as possible.
|
16 jaren geleden |
tcycle_down.asy
|
bb70144d49
Center all <InstName> attributes on the symbols.
|
16 jaren geleden |
tcycle_test.asc
|
71b63dac86
Label all nodes meaningfully as possible.
|
16 jaren geleden |
tcycle_test.plt
|
6bace237a7
Add cycle up gate, and add it to the tcycle_test test circuit.
|
16 jaren geleden |
tcycle_up.asc
|
71b63dac86
Label all nodes meaningfully as possible.
|
16 jaren geleden |
tcycle_up.asy
|
bb70144d49
Center all <InstName> attributes on the symbols.
|
16 jaren geleden |
tg.asc
|
6947b90592
Improve reference designator names for dtflop-ms and
|
16 jaren geleden |
tg.asy
|
bb70144d49
Center all <InstName> attributes on the symbols.
|
16 jaren geleden |
tg_test.asc
|
ce05b26851
Add a working 3:1 multiplexer of custom design, using CMOS t-gates.
|
16 jaren geleden |
tg_test.plt
|
1f8779e9f7
Test the transmission gate (and it works).
|
16 jaren geleden |
tinv.asc
|
6d672e75f9
Changed 10k to 12k pull-middle resistors in all gates.
|
16 jaren geleden |
tinv.asy
|
bb70144d49
Center all <InstName> attributes on the symbols.
|
16 jaren geleden |
tinv_test.asc
|
f0376bfa82
Use better node and part names.
|
16 jaren geleden |
tinv_test.plt
|
733954ace9
Change the remaining circuits from microsecond to nanoscale time scale,
|
16 jaren geleden |
tnand.asc
|
3ed865b929
Support translating the 'tnand' subcircuit using bb.py.
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16 jaren geleden |
tnand.asy
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516ea2a9b9
Add "3" to symbol dyadic gates, so it is clearer that they are trinary.
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16 jaren geleden |
tnand3.asc
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71b63dac86
Label all nodes meaningfully as possible.
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16 jaren geleden |
tnand3.asy
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bb70144d49
Center all <InstName> attributes on the symbols.
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16 jaren geleden |
tnand_test.asc
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7d6aff9338
Add MAX gate (inverted TNOR), untested.
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16 jaren geleden |
tnand_test.plt
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733954ace9
Change the remaining circuits from microsecond to nanoscale time scale,
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16 jaren geleden |
tnor.asc
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cf170ccdf2
In tnor, label all nodes usefully.
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16 jaren geleden |
tnor.asy
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516ea2a9b9
Add "3" to symbol dyadic gates, so it is clearer that they are trinary.
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16 jaren geleden |
tnor3.asc
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71b63dac86
Label all nodes meaningfully as possible.
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16 jaren geleden |
tnor3.asy
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bb70144d49
Center all <InstName> attributes on the symbols.
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16 jaren geleden |
tnor3_test.asc
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71b63dac86
Label all nodes meaningfully as possible.
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16 jaren geleden |
tnor3_test.plt
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733954ace9
Change the remaining circuits from microsecond to nanoscale time scale,
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16 jaren geleden |
tnor_test.asc
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7d6aff9338
Add MAX gate (inverted TNOR), untested.
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16 jaren geleden |
tnor_test.plt
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733954ace9
Change the remaining circuits from microsecond to nanoscale time scale,
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16 jaren geleden |
tpower.asc
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028cd72fb4
Add LTSpice circuits and symbols for D-type latch, PZN tri-flop,
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16 jaren geleden |
tpower.asy
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028cd72fb4
Add LTSpice circuits and symbols for D-type latch, PZN tri-flop,
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16 jaren geleden |
tpower_test.asc
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21b41aea34
Connect PMOS and NMOS bodies to Vdd and Vss, so the body effect will be taken
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16 jaren geleden |
trit-0.asc
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c9971298c3
Name sp3t-{1,2,3} subcircuits in trit-{i,0,1} as sw_{i,0,1}, to easily distinguish.
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16 jaren geleden |
trit-0.asy
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d002756e2c
Make trit-X files for i,0,1; which look like switches set to either i, 0, or 1.
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16 jaren geleden |
trit-1.asc
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c9971298c3
Name sp3t-{1,2,3} subcircuits in trit-{i,0,1} as sw_{i,0,1}, to easily distinguish.
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16 jaren geleden |
trit-1.asy
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d002756e2c
Make trit-X files for i,0,1; which look like switches set to either i, 0, or 1.
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16 jaren geleden |
trit-i.asc
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c9971298c3
Name sp3t-{1,2,3} subcircuits in trit-{i,0,1} as sw_{i,0,1}, to easily distinguish.
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16 jaren geleden |
trit-i.asy
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d002756e2c
Make trit-X files for i,0,1; which look like switches set to either i, 0, or 1.
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16 jaren geleden |
trit_reg3.asc
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ad1756634f
In dtflop-msmo_test, show how dtflop-msmo and dtflop-ms2 differ.
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16 jaren geleden |
trit_reg3.asy
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f54c7ee726
Change trit_reg3 (and therefore main) to use dtflop_ms, instead of dtflop_ms2.
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16 jaren geleden |
trit_reg3_test.asc
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ad1756634f
In dtflop-msmo_test, show how dtflop-msmo and dtflop-ms2 differ.
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16 jaren geleden |
trit_reg3_test.plt
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b4e92805c2
Annonate the trit_reg3_test graph, which doesn't match http://jeff.tk/wiki/Image:3-Trit_Register_Timing_Diagram.png.
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16 jaren geleden |
trit_test.asc
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695ef87e1c
Fix sp3t-2, so that trit_test correctly simulates and finds the operating points.
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16 jaren geleden |
tsign3.asc
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3e7c242041
Add 4-trit sign detector, rename 3-trit one to tsign3.
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16 jaren geleden |
tsign3.asy
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3e7c242041
Add 4-trit sign detector, rename 3-trit one to tsign3.
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16 jaren geleden |
tsign4.asc
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3e7c242041
Add 4-trit sign detector, rename 3-trit one to tsign3.
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16 jaren geleden |
tsign4.asy
|
3e7c242041
Add 4-trit sign detector, rename 3-trit one to tsign3.
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16 jaren geleden |
tsign_test.asc
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149605f08a
Sign detector board: use resistor network (PCB not laid out).
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16 jaren geleden |
tsign_test.plt
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9a65ad934c
tsign_test: only test 4-trit sign detector.
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16 jaren geleden |
ttlatch.asc
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71b63dac86
Label all nodes meaningfully as possible.
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16 jaren geleden |
ttlatch.asy
|
f6fbb1ff28
Add T-type tri-latch with PZN inputs (untested).
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16 jaren geleden |
ttlatch_test.asc
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a41b2905f7
Fix ttlatch, one of the inputs to a TNOR3 was miswired.
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16 jaren geleden |
ttlatch_test.plt
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253ebea37d
At least the P, Z, and N inputs of ttlatch appear to work, when T=i. Have not
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16 jaren geleden |