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circuits
Jeff Connelly d46c59be12 Shorten simulation time by 5/2 for clock_gen_test. %!s(int64=16) %!d(string=hai) anos
..
.gitignore 3010cc7892 Permissions Changes %!s(int64=16) %!d(string=hai) anos
INPUT_A.txt 733954ace9 Change the remaining circuits from microsecond to nanoscale time scale, %!s(int64=16) %!d(string=hai) anos
INPUT_B.txt 733954ace9 Change the remaining circuits from microsecond to nanoscale time scale, %!s(int64=16) %!d(string=hai) anos
alu-fast.asc 8bf16f88b2 The behavioral ALU model, alu-fast, now works. %!s(int64=16) %!d(string=hai) anos
alu-fast.asy d14abb6cf0 Add alu-fast, a behavorial model of a comparing ALU. Not working. %!s(int64=16) %!d(string=hai) anos
alu-fast_test.asc a0643e4f62 Partially fix alu, by slowing down the transitions. %!s(int64=16) %!d(string=hai) anos
alu-fast_test.plt 8bf16f88b2 The behavioral ALU model, alu-fast, now works. %!s(int64=16) %!d(string=hai) anos
alu.asc 05c7b1ee58 Improve names of components in main.asc and alu.asc. %!s(int64=16) %!d(string=hai) anos
alu.asy 400a66a116 Fix the ALU and properly test it (including difference, not just sign output). %!s(int64=16) %!d(string=hai) anos
alu_test.asc 400a66a116 Fix the ALU and properly test it (including difference, not just sign output). %!s(int64=16) %!d(string=hai) anos
alu_test.plt 400a66a116 Fix the ALU and properly test it (including difference, not just sign output). %!s(int64=16) %!d(string=hai) anos
clock_gen-fast.asc 6c1cb50931 Update comments about clock gen. %!s(int64=16) %!d(string=hai) anos
clock_gen-fast.asy 3f171c1e01 Move the inverter out of the clock generator (both versions) and into main. %!s(int64=16) %!d(string=hai) anos
clock_gen-fast_test.asc 7eaa408938 Rename clock_gen with PULSE voltage source to clock_gen-fast, since it is. %!s(int64=16) %!d(string=hai) anos
clock_gen-fast_test.plt 7eaa408938 Rename clock_gen with PULSE voltage source to clock_gen-fast, since it is. %!s(int64=16) %!d(string=hai) anos
clock_gen.asc 6c1cb50931 Update comments about clock gen. %!s(int64=16) %!d(string=hai) anos
clock_gen.asy 3f171c1e01 Move the inverter out of the clock generator (both versions) and into main. %!s(int64=16) %!d(string=hai) anos
clock_gen_test.asc d46c59be12 Shorten simulation time by 5/2 for clock_gen_test. %!s(int64=16) %!d(string=hai) anos
clock_gen_test.plt 588d5f2c54 Fix clock_gen_test.asc file. %!s(int64=16) %!d(string=hai) anos
control_parts.asc 31b02a7555 Correctly name the 1:3 decoder (was incorrectly named as a 3:1 decoder). %!s(int64=16) %!d(string=hai) anos
cycle_up_instance.asc 22d54879f8 Add instances of cycle_up, decoder, inverter, and min used for logic board creation. %!s(int64=16) %!d(string=hai) anos
decoder1-3.asc 873fda810b Add notes about more efficient implementations of 1:3 decoder and 9:3 mux. %!s(int64=16) %!d(string=hai) anos
decoder1-3.asy 31b02a7555 Correctly name the 1:3 decoder (was incorrectly named as a 3:1 decoder). %!s(int64=16) %!d(string=hai) anos
decoder1-3_test.asc 31b02a7555 Correctly name the 1:3 decoder (was incorrectly named as a 3:1 decoder). %!s(int64=16) %!d(string=hai) anos
decoder1-3_test.plt 31b02a7555 Correctly name the 1:3 decoder (was incorrectly named as a 3:1 decoder). %!s(int64=16) %!d(string=hai) anos
decoder_instance.asc 22d54879f8 Add instances of cycle_up, decoder, inverter, and min used for logic board creation. %!s(int64=16) %!d(string=hai) anos
diode_test.asc dc2be664ad Add symbols, subcircuits, and a test circuit for FD and RD Gates. %!s(int64=16) %!d(string=hai) anos
diode_test.plt 2f6225f905 Save plot settings for FD and RD gates. %!s(int64=16) %!d(string=hai) anos
dtflop-et.asc 53434f58d9 In the latches and flip-flop, use diagonal wires for the cross-coupled %!s(int64=16) %!d(string=hai) anos
dtflop-et.asy 4b5888b176 Add an attempt at an edge-triggered D flip-flop, using an inverter and %!s(int64=16) %!d(string=hai) anos
dtflop-et_test.asc 4b5888b176 Add an attempt at an edge-triggered D flip-flop, using an inverter and %!s(int64=16) %!d(string=hai) anos
dtflop-et_test.plt 4b5888b176 Add an attempt at an edge-triggered D flip-flop, using an inverter and %!s(int64=16) %!d(string=hai) anos
dtflop-ms2.asc 71b63dac86 Label all nodes meaningfully as possible. %!s(int64=16) %!d(string=hai) anos
dtflop-ms2.asy 998662b26f Rename dtflop-et-ms to dtflop-ms2, everywhere. %!s(int64=16) %!d(string=hai) anos
dtflop-ms2_test.asc 650c5bfbb8 Export dtflop-ms2_test to SPICE netlist, with better node names. %!s(int64=16) %!d(string=hai) anos
dtflop-ms2_test.plt 998662b26f Rename dtflop-et-ms to dtflop-ms2, everywhere. %!s(int64=16) %!d(string=hai) anos
dtflop-msmo.asc 07d9594910 Rename dtflop-ms to dtflop-msmo (for Mouftah), since it has drawbacks. %!s(int64=16) %!d(string=hai) anos
dtflop-msmo.asy 07d9594910 Rename dtflop-ms to dtflop-msmo (for Mouftah), since it has drawbacks. %!s(int64=16) %!d(string=hai) anos
dtflop-msmo_test.asc ad1756634f In dtflop-msmo_test, show how dtflop-msmo and dtflop-ms2 differ. %!s(int64=16) %!d(string=hai) anos
dtflop-msmo_test.plt ad1756634f In dtflop-msmo_test, show how dtflop-msmo and dtflop-ms2 differ. %!s(int64=16) %!d(string=hai) anos
dtflop.asc 71b63dac86 Label all nodes meaningfully as possible. %!s(int64=16) %!d(string=hai) anos
dtflop.asy bb70144d49 Center all <InstName> attributes on the symbols. %!s(int64=16) %!d(string=hai) anos
dtflop2.asc 70fba43cc3 Add synchronous inputs to dtflop2, an experimental D-type tri-flop %!s(int64=16) %!d(string=hai) anos
dtflop2.asy 70fba43cc3 Add synchronous inputs to dtflop2, an experimental D-type tri-flop %!s(int64=16) %!d(string=hai) anos
dtflop2_test.asc 70fba43cc3 Add synchronous inputs to dtflop2, an experimental D-type tri-flop %!s(int64=16) %!d(string=hai) anos
dtflop2_test.plt 45a448c109 Add an experimental D-type flip-flop with asynchronous inputs. Not tested. %!s(int64=16) %!d(string=hai) anos
dtflop_test.asc 92f42f8e74 Add a power supply to the D-type flip-flop test circuit, and change it to %!s(int64=16) %!d(string=hai) anos
dtflop_test.plt 92f42f8e74 Add a power supply to the D-type flip-flop test circuit, and change it to %!s(int64=16) %!d(string=hai) anos
dtlatch.asc 71b63dac86 Label all nodes meaningfully as possible. %!s(int64=16) %!d(string=hai) anos
dtlatch.asy bb70144d49 Center all <InstName> attributes on the symbols. %!s(int64=16) %!d(string=hai) anos
dtlatch_test.asc 28ef9619ca Add a ring oscillator, built with 17 simple ternary inverters, that %!s(int64=16) %!d(string=hai) anos
dtlatch_test.plt 46ff8bc067 Add saved plot settings for dtflop and dtlatch, so that after simulating, %!s(int64=16) %!d(string=hai) anos
fd.asc 597752acff Restore FD and RD to D model again since it works, update 1/2 + & - plot settings. %!s(int64=16) %!d(string=hai) anos
fd.asy dc2be664ad Add symbols, subcircuits, and a test circuit for FD and RD Gates. %!s(int64=16) %!d(string=hai) anos
full_adder.asc 31b02a7555 Correctly name the 1:3 decoder (was incorrectly named as a 3:1 decoder). %!s(int64=16) %!d(string=hai) anos
full_adder.asy 971558aaf5 Add a full-adder, based on the design by Srivastava and Venkatapathy %!s(int64=16) %!d(string=hai) anos
full_adder_test.asc 557cc77e90 Name *-test.* to *_test.*, for consistency. %!s(int64=16) %!d(string=hai) anos
full_adder_test.plt 557cc77e90 Name *-test.* to *_test.*, for consistency. %!s(int64=16) %!d(string=hai) anos
half_adder.asc 0971f08b1e Use the fd and rd subcircuits in the half-adder, breaking it. %!s(int64=16) %!d(string=hai) anos
half_adder.asy 012e129f7f Rename adder to half_adder. %!s(int64=16) %!d(string=hai) anos
half_adder_test.asc 012e129f7f Rename adder to half_adder. %!s(int64=16) %!d(string=hai) anos
half_adder_test.plt 597752acff Restore FD and RD to D model again since it works, update 1/2 + & - plot settings. %!s(int64=16) %!d(string=hai) anos
half_subtractor.asc 3ab16959f2 Add a half-working half-subtractor. %!s(int64=16) %!d(string=hai) anos
half_subtractor.asy 3ab16959f2 Add a half-working half-subtractor. %!s(int64=16) %!d(string=hai) anos
half_subtractor_test.asc 3ab16959f2 Add a half-working half-subtractor. %!s(int64=16) %!d(string=hai) anos
half_subtractor_test.plt 597752acff Restore FD and RD to D model again since it works, update 1/2 + & - plot settings. %!s(int64=16) %!d(string=hai) anos
input_n.txt 733954ace9 Change the remaining circuits from microsecond to nanoscale time scale, %!s(int64=16) %!d(string=hai) anos
input_p.txt 733954ace9 Change the remaining circuits from microsecond to nanoscale time scale, %!s(int64=16) %!d(string=hai) anos
input_z.txt 733954ace9 Change the remaining circuits from microsecond to nanoscale time scale, %!s(int64=16) %!d(string=hai) anos
inverter_instance.asc 22d54879f8 Add instances of cycle_up, decoder, inverter, and min used for logic board creation. %!s(int64=16) %!d(string=hai) anos
logic_board.asc d616e5a932 Logic board: add 4 buffers (need 3 for ALU), and remove 3 tinv's to save space. %!s(int64=16) %!d(string=hai) anos
main.asc 3f171c1e01 Move the inverter out of the clock generator (both versions) and into main. %!s(int64=16) %!d(string=hai) anos
main.plt 3f171c1e01 Move the inverter out of the clock generator (both versions) and into main. %!s(int64=16) %!d(string=hai) anos
main_cmptest.asc 74ee971842 Add main architecture with cmptest instruction. %!s(int64=16) %!d(string=hai) anos
main_cmptest.plt 74ee971842 Add main architecture with cmptest instruction. %!s(int64=16) %!d(string=hai) anos
main_jmptest.asc 376ea0d90d Split main to main-jmptest, and add swrom-jmptest. %!s(int64=16) %!d(string=hai) anos
main_jmptest.plt 376ea0d90d Split main to main-jmptest, and add swrom-jmptest. %!s(int64=16) %!d(string=hai) anos
main_lwitest.asc ea1ae44eb0 TCA0 (main_lwitest): replace with latest TCA2 architecture, but without BE and CMP. %!s(int64=16) %!d(string=hai) anos
main_lwitest.plt ea1ae44eb0 TCA0 (main_lwitest): replace with latest TCA2 architecture, but without BE and CMP. %!s(int64=16) %!d(string=hai) anos
max.asc 71b63dac86 Label all nodes meaningfully as possible. %!s(int64=16) %!d(string=hai) anos
max.asy 516ea2a9b9 Add "3" to symbol dyadic gates, so it is clearer that they are trinary. %!s(int64=16) %!d(string=hai) anos
min.asc 71b63dac86 Label all nodes meaningfully as possible. %!s(int64=16) %!d(string=hai) anos
min.asy 516ea2a9b9 Add "3" to symbol dyadic gates, so it is clearer that they are trinary. %!s(int64=16) %!d(string=hai) anos
min_instance.asc 22d54879f8 Add instances of cycle_up, decoder, inverter, and min used for logic board creation. %!s(int64=16) %!d(string=hai) anos
mux3-1.asc 31b02a7555 Correctly name the 1:3 decoder (was incorrectly named as a 3:1 decoder). %!s(int64=16) %!d(string=hai) anos
mux3-1.asy ef789bccc2 In the 3:1 mux, move the S input within the symbol. %!s(int64=16) %!d(string=hai) anos
mux3-1_test.asc b0a37135fd Changed name of power supplies in mux3-1_test.asc %!s(int64=16) %!d(string=hai) anos
mux3-1_test.plt a925a08992 Save plot settings for 3:1 mux. %!s(int64=16) %!d(string=hai) anos
mux9-3.asc 873fda810b Add notes about more efficient implementations of 1:3 decoder and 9:3 mux. %!s(int64=16) %!d(string=hai) anos
mux9-3.asy 06feb8e046 Add swrom (untested). %!s(int64=16) %!d(string=hai) anos
nti.asc 6947b90592 Improve reference designator names for dtflop-ms and %!s(int64=16) %!d(string=hai) anos
nti.asy bb70144d49 Center all <InstName> attributes on the symbols. %!s(int64=16) %!d(string=hai) anos
pti.asc 6947b90592 Improve reference designator names for dtflop-ms and %!s(int64=16) %!d(string=hai) anos
pti.asy bb70144d49 Center all <InstName> attributes on the symbols. %!s(int64=16) %!d(string=hai) anos
pznflop.asc 71b63dac86 Label all nodes meaningfully as possible. %!s(int64=16) %!d(string=hai) anos
pznflop.asy 7895ecef8d PZN tri-flop, untested (second try). %!s(int64=16) %!d(string=hai) anos
pznflop_test.asc 057f8ef746 Demonstrate that pznflop (clocked) functions correctly, now that tnand3 is fixed. %!s(int64=16) %!d(string=hai) anos
pznflop_test.plt 057f8ef746 Demonstrate that pznflop (clocked) functions correctly, now that tnand3 is fixed. %!s(int64=16) %!d(string=hai) anos
pznlatch.asc 53434f58d9 In the latches and flip-flop, use diagonal wires for the cross-coupled %!s(int64=16) %!d(string=hai) anos
pznlatch.asy 61fe926297 Add clocked PZN flip-flop, untested. %!s(int64=16) %!d(string=hai) anos
pznlatch_test.asc f03b5e831a Rename pznflop to pznlatch, because one common convention now dictates that %!s(int64=16) %!d(string=hai) anos
pznlatch_test.plt f03b5e831a Rename pznflop to pznlatch, because one common convention now dictates that %!s(int64=16) %!d(string=hai) anos
rd.asc 597752acff Restore FD and RD to D model again since it works, update 1/2 + & - plot settings. %!s(int64=16) %!d(string=hai) anos
rd.asy dc2be664ad Add symbols, subcircuits, and a test circuit for FD and RD Gates. %!s(int64=16) %!d(string=hai) anos
ring_oscillator.asc 093a58aeba Remove a spurious net label. %!s(int64=16) %!d(string=hai) anos
ring_oscillator.plt 6e6a66c88b Make a ring oscillator with a TNAND gate to initialize it. Original %!s(int64=16) %!d(string=hai) anos
ring_oscillator_with_ic.asc 6e6a66c88b Make a ring oscillator with a TNAND gate to initialize it. Original %!s(int64=16) %!d(string=hai) anos
shift_down.asc 989124e47e Add shift down gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. %!s(int64=16) %!d(string=hai) anos
shift_down.asy 989124e47e Add shift down gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. %!s(int64=16) %!d(string=hai) anos
shift_test.asc 989124e47e Add shift down gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. %!s(int64=16) %!d(string=hai) anos
shift_test.plt 989124e47e Add shift down gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. %!s(int64=16) %!d(string=hai) anos
shift_up.asc 989124e47e Add shift down gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. %!s(int64=16) %!d(string=hai) anos
shift_up.asy d80e93413b Add a shift up gate built using Mouftah's gates (untested). %!s(int64=16) %!d(string=hai) anos
sp3t-1.asc d002756e2c Make trit-X files for i,0,1; which look like switches set to either i, 0, or 1. %!s(int64=16) %!d(string=hai) anos
sp3t-1.asy f41deba04b Reorder SP3T models pin tables to match the NKK SS14M SP3T switches. %!s(int64=16) %!d(string=hai) anos
sp3t-2.asc 695ef87e1c Fix sp3t-2, so that trit_test correctly simulates and finds the operating points. %!s(int64=16) %!d(string=hai) anos
sp3t-2.asy f41deba04b Reorder SP3T models pin tables to match the NKK SS14M SP3T switches. %!s(int64=16) %!d(string=hai) anos
sp3t-3.asc d002756e2c Make trit-X files for i,0,1; which look like switches set to either i, 0, or 1. %!s(int64=16) %!d(string=hai) anos
sp3t-3.asy f41deba04b Reorder SP3T models pin tables to match the NKK SS14M SP3T switches. %!s(int64=16) %!d(string=hai) anos
sp3t_test.asc d002756e2c Make trit-X files for i,0,1; which look like switches set to either i, 0, or 1. %!s(int64=16) %!d(string=hai) anos
sti.asc 71b63dac86 Label all nodes meaningfully as possible. %!s(int64=16) %!d(string=hai) anos
sti.asy bb70144d49 Center all <InstName> attributes on the symbols. %!s(int64=16) %!d(string=hai) anos
swrom-blank.asc 707e1376d2 Replace sp3t with trit-0 in swrom-blank. New models. %!s(int64=16) %!d(string=hai) anos
swrom-cmptest.asc 47ba6e4f70 Add cmptest, to test the CMP instruction. %!s(int64=16) %!d(string=hai) anos
swrom-cmptest.asy 47ba6e4f70 Add cmptest, to test the CMP instruction. %!s(int64=16) %!d(string=hai) anos
swrom-fast.asc 6079843376 Change swrom-fast symbol to use i, 0, and 1 instead of 0, 1, 2, %!s(int64=16) %!d(string=hai) anos
swrom-fast.asy e4b28cbfee Add symbol and test for behavorial model of 3x3 SWROM with guess.t loaded. %!s(int64=16) %!d(string=hai) anos
swrom-fast_test.asc ffe64e5f80 Change swrom-fast to accept a program given on the top-level %!s(int64=16) %!d(string=hai) anos
swrom-fast_test.plt e4b28cbfee Add symbol and test for behavorial model of 3x3 SWROM with guess.t loaded. %!s(int64=16) %!d(string=hai) anos
swrom-guess.asc 4acda26f9c Add swrom loaded with guess.t. %!s(int64=16) %!d(string=hai) anos
swrom-guess.asy 4acda26f9c Add swrom loaded with guess.t. %!s(int64=16) %!d(string=hai) anos
swrom-jmptest.asc 376ea0d90d Split main to main-jmptest, and add swrom-jmptest. %!s(int64=16) %!d(string=hai) anos
swrom-jmptest.asy 376ea0d90d Split main to main-jmptest, and add swrom-jmptest. %!s(int64=16) %!d(string=hai) anos
swrom-lwitest.asc 12af1d5bce Add swrom-lwitest, a switch-ROM with lwitest.3 loaded, and %!s(int64=16) %!d(string=hai) anos
swrom-lwitest.asy 12af1d5bce Add swrom-lwitest, a switch-ROM with lwitest.3 loaded, and %!s(int64=16) %!d(string=hai) anos
swrom.asc 376ea0d90d Split main to main-jmptest, and add swrom-jmptest. %!s(int64=16) %!d(string=hai) anos
swrom.asy 9fc48c519a Change switch-ROM bits (from asm/guess.t assembled) to use $G_Vss and $G_Vdd, %!s(int64=16) %!d(string=hai) anos
swrom_test.asc 9fc48c519a Change switch-ROM bits (from asm/guess.t assembled) to use $G_Vss and $G_Vdd, %!s(int64=16) %!d(string=hai) anos
swrom_test.plt 78486c24b1 Clean up: remove Draft2 circuit, add v(address) to swrom_test.plt. %!s(int64=16) %!d(string=hai) anos
tbuf.asc 1c0cd268e8 Add a new tbuf subcircuit, two simple ternary inverters. %!s(int64=16) %!d(string=hai) anos
tbuf.asy 1c0cd268e8 Add a new tbuf subcircuit, two simple ternary inverters. %!s(int64=16) %!d(string=hai) anos
tcycle_down.asc 71b63dac86 Label all nodes meaningfully as possible. %!s(int64=16) %!d(string=hai) anos
tcycle_down.asy bb70144d49 Center all <InstName> attributes on the symbols. %!s(int64=16) %!d(string=hai) anos
tcycle_test.asc 71b63dac86 Label all nodes meaningfully as possible. %!s(int64=16) %!d(string=hai) anos
tcycle_test.plt 6bace237a7 Add cycle up gate, and add it to the tcycle_test test circuit. %!s(int64=16) %!d(string=hai) anos
tcycle_up.asc 71b63dac86 Label all nodes meaningfully as possible. %!s(int64=16) %!d(string=hai) anos
tcycle_up.asy bb70144d49 Center all <InstName> attributes on the symbols. %!s(int64=16) %!d(string=hai) anos
tg.asc 6947b90592 Improve reference designator names for dtflop-ms and %!s(int64=16) %!d(string=hai) anos
tg.asy bb70144d49 Center all <InstName> attributes on the symbols. %!s(int64=16) %!d(string=hai) anos
tg_test.asc ce05b26851 Add a working 3:1 multiplexer of custom design, using CMOS t-gates. %!s(int64=16) %!d(string=hai) anos
tg_test.plt 1f8779e9f7 Test the transmission gate (and it works). %!s(int64=16) %!d(string=hai) anos
tinv.asc 6d672e75f9 Changed 10k to 12k pull-middle resistors in all gates. %!s(int64=16) %!d(string=hai) anos
tinv.asy bb70144d49 Center all <InstName> attributes on the symbols. %!s(int64=16) %!d(string=hai) anos
tinv_test.asc f0376bfa82 Use better node and part names. %!s(int64=16) %!d(string=hai) anos
tinv_test.plt 733954ace9 Change the remaining circuits from microsecond to nanoscale time scale, %!s(int64=16) %!d(string=hai) anos
tnand.asc 3ed865b929 Support translating the 'tnand' subcircuit using bb.py. %!s(int64=16) %!d(string=hai) anos
tnand.asy 516ea2a9b9 Add "3" to symbol dyadic gates, so it is clearer that they are trinary. %!s(int64=16) %!d(string=hai) anos
tnand3.asc 71b63dac86 Label all nodes meaningfully as possible. %!s(int64=16) %!d(string=hai) anos
tnand3.asy bb70144d49 Center all <InstName> attributes on the symbols. %!s(int64=16) %!d(string=hai) anos
tnand_test.asc 7d6aff9338 Add MAX gate (inverted TNOR), untested. %!s(int64=16) %!d(string=hai) anos
tnand_test.plt 733954ace9 Change the remaining circuits from microsecond to nanoscale time scale, %!s(int64=16) %!d(string=hai) anos
tnor.asc cf170ccdf2 In tnor, label all nodes usefully. %!s(int64=16) %!d(string=hai) anos
tnor.asy 516ea2a9b9 Add "3" to symbol dyadic gates, so it is clearer that they are trinary. %!s(int64=16) %!d(string=hai) anos
tnor3.asc 71b63dac86 Label all nodes meaningfully as possible. %!s(int64=16) %!d(string=hai) anos
tnor3.asy bb70144d49 Center all <InstName> attributes on the symbols. %!s(int64=16) %!d(string=hai) anos
tnor3_test.asc 71b63dac86 Label all nodes meaningfully as possible. %!s(int64=16) %!d(string=hai) anos
tnor3_test.plt 733954ace9 Change the remaining circuits from microsecond to nanoscale time scale, %!s(int64=16) %!d(string=hai) anos
tnor_test.asc 7d6aff9338 Add MAX gate (inverted TNOR), untested. %!s(int64=16) %!d(string=hai) anos
tnor_test.plt 733954ace9 Change the remaining circuits from microsecond to nanoscale time scale, %!s(int64=16) %!d(string=hai) anos
tpower.asc 028cd72fb4 Add LTSpice circuits and symbols for D-type latch, PZN tri-flop, %!s(int64=16) %!d(string=hai) anos
tpower.asy 028cd72fb4 Add LTSpice circuits and symbols for D-type latch, PZN tri-flop, %!s(int64=16) %!d(string=hai) anos
tpower_test.asc 21b41aea34 Connect PMOS and NMOS bodies to Vdd and Vss, so the body effect will be taken %!s(int64=16) %!d(string=hai) anos
trit-0.asc c9971298c3 Name sp3t-{1,2,3} subcircuits in trit-{i,0,1} as sw_{i,0,1}, to easily distinguish. %!s(int64=16) %!d(string=hai) anos
trit-0.asy d002756e2c Make trit-X files for i,0,1; which look like switches set to either i, 0, or 1. %!s(int64=16) %!d(string=hai) anos
trit-1.asc c9971298c3 Name sp3t-{1,2,3} subcircuits in trit-{i,0,1} as sw_{i,0,1}, to easily distinguish. %!s(int64=16) %!d(string=hai) anos
trit-1.asy d002756e2c Make trit-X files for i,0,1; which look like switches set to either i, 0, or 1. %!s(int64=16) %!d(string=hai) anos
trit-i.asc c9971298c3 Name sp3t-{1,2,3} subcircuits in trit-{i,0,1} as sw_{i,0,1}, to easily distinguish. %!s(int64=16) %!d(string=hai) anos
trit-i.asy d002756e2c Make trit-X files for i,0,1; which look like switches set to either i, 0, or 1. %!s(int64=16) %!d(string=hai) anos
trit_reg3.asc ad1756634f In dtflop-msmo_test, show how dtflop-msmo and dtflop-ms2 differ. %!s(int64=16) %!d(string=hai) anos
trit_reg3.asy f54c7ee726 Change trit_reg3 (and therefore main) to use dtflop_ms, instead of dtflop_ms2. %!s(int64=16) %!d(string=hai) anos
trit_reg3_test.asc ad1756634f In dtflop-msmo_test, show how dtflop-msmo and dtflop-ms2 differ. %!s(int64=16) %!d(string=hai) anos
trit_reg3_test.plt b4e92805c2 Annonate the trit_reg3_test graph, which doesn't match http://jeff.tk/wiki/Image:3-Trit_Register_Timing_Diagram.png. %!s(int64=16) %!d(string=hai) anos
trit_test.asc 695ef87e1c Fix sp3t-2, so that trit_test correctly simulates and finds the operating points. %!s(int64=16) %!d(string=hai) anos
tsign3.asc 3e7c242041 Add 4-trit sign detector, rename 3-trit one to tsign3. %!s(int64=16) %!d(string=hai) anos
tsign3.asy 3e7c242041 Add 4-trit sign detector, rename 3-trit one to tsign3. %!s(int64=16) %!d(string=hai) anos
tsign4.asc 3e7c242041 Add 4-trit sign detector, rename 3-trit one to tsign3. %!s(int64=16) %!d(string=hai) anos
tsign4.asy 3e7c242041 Add 4-trit sign detector, rename 3-trit one to tsign3. %!s(int64=16) %!d(string=hai) anos
tsign_test.asc 149605f08a Sign detector board: use resistor network (PCB not laid out). %!s(int64=16) %!d(string=hai) anos
tsign_test.plt 9a65ad934c tsign_test: only test 4-trit sign detector. %!s(int64=16) %!d(string=hai) anos
ttlatch.asc 71b63dac86 Label all nodes meaningfully as possible. %!s(int64=16) %!d(string=hai) anos
ttlatch.asy f6fbb1ff28 Add T-type tri-latch with PZN inputs (untested). %!s(int64=16) %!d(string=hai) anos
ttlatch_test.asc a41b2905f7 Fix ttlatch, one of the inputs to a TNOR3 was miswired. %!s(int64=16) %!d(string=hai) anos
ttlatch_test.plt 253ebea37d At least the P, Z, and N inputs of ttlatch appear to work, when T=i. Have not %!s(int64=16) %!d(string=hai) anos