| .. |
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.gitignore
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3010cc7892
Permissions Changes
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16 gadi atpakaļ |
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INPUT_A.txt
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733954ace9
Change the remaining circuits from microsecond to nanoscale time scale,
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16 gadi atpakaļ |
|
INPUT_B.txt
|
733954ace9
Change the remaining circuits from microsecond to nanoscale time scale,
|
16 gadi atpakaļ |
|
alu-fast.asc
|
8bf16f88b2
The behavioral ALU model, alu-fast, now works.
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16 gadi atpakaļ |
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alu-fast.asy
|
d14abb6cf0
Add alu-fast, a behavorial model of a comparing ALU. Not working.
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16 gadi atpakaļ |
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alu-fast_test.asc
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a0643e4f62
Partially fix alu, by slowing down the transitions.
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16 gadi atpakaļ |
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alu-fast_test.plt
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8bf16f88b2
The behavioral ALU model, alu-fast, now works.
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16 gadi atpakaļ |
|
alu.asc
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05c7b1ee58
Improve names of components in main.asc and alu.asc.
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16 gadi atpakaļ |
|
alu.asy
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400a66a116
Fix the ALU and properly test it (including difference, not just sign output).
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16 gadi atpakaļ |
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alu_test.asc
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400a66a116
Fix the ALU and properly test it (including difference, not just sign output).
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16 gadi atpakaļ |
|
alu_test.plt
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400a66a116
Fix the ALU and properly test it (including difference, not just sign output).
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16 gadi atpakaļ |
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clock_gen-fast.asc
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6c1cb50931
Update comments about clock gen.
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16 gadi atpakaļ |
|
clock_gen-fast.asy
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3f171c1e01
Move the inverter out of the clock generator (both versions) and into main.
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16 gadi atpakaļ |
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clock_gen-fast_test.asc
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7eaa408938
Rename clock_gen with PULSE voltage source to clock_gen-fast, since it is.
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16 gadi atpakaļ |
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clock_gen-fast_test.plt
|
7eaa408938
Rename clock_gen with PULSE voltage source to clock_gen-fast, since it is.
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16 gadi atpakaļ |
|
clock_gen.asc
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6c1cb50931
Update comments about clock gen.
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16 gadi atpakaļ |
|
clock_gen.asy
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3f171c1e01
Move the inverter out of the clock generator (both versions) and into main.
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16 gadi atpakaļ |
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clock_gen_test.asc
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d46c59be12
Shorten simulation time by 5/2 for clock_gen_test.
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16 gadi atpakaļ |
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clock_gen_test.plt
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588d5f2c54
Fix clock_gen_test.asc file.
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16 gadi atpakaļ |
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control_parts.asc
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31b02a7555
Correctly name the 1:3 decoder (was incorrectly named as a 3:1 decoder).
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16 gadi atpakaļ |
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cycle_up_instance.asc
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22d54879f8
Add instances of cycle_up, decoder, inverter, and min used for logic board creation.
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16 gadi atpakaļ |
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decoder1-3.asc
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873fda810b
Add notes about more efficient implementations of 1:3 decoder and 9:3 mux.
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16 gadi atpakaļ |
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decoder1-3.asy
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31b02a7555
Correctly name the 1:3 decoder (was incorrectly named as a 3:1 decoder).
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16 gadi atpakaļ |
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decoder1-3_test.asc
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31b02a7555
Correctly name the 1:3 decoder (was incorrectly named as a 3:1 decoder).
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16 gadi atpakaļ |
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decoder1-3_test.plt
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31b02a7555
Correctly name the 1:3 decoder (was incorrectly named as a 3:1 decoder).
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16 gadi atpakaļ |
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decoder_instance.asc
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22d54879f8
Add instances of cycle_up, decoder, inverter, and min used for logic board creation.
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16 gadi atpakaļ |
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diode_test.asc
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dc2be664ad
Add symbols, subcircuits, and a test circuit for FD and RD Gates.
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16 gadi atpakaļ |
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diode_test.plt
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2f6225f905
Save plot settings for FD and RD gates.
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16 gadi atpakaļ |
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dtflop-et.asc
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53434f58d9
In the latches and flip-flop, use diagonal wires for the cross-coupled
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16 gadi atpakaļ |
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dtflop-et.asy
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4b5888b176
Add an attempt at an edge-triggered D flip-flop, using an inverter and
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16 gadi atpakaļ |
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dtflop-et_test.asc
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4b5888b176
Add an attempt at an edge-triggered D flip-flop, using an inverter and
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16 gadi atpakaļ |
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dtflop-et_test.plt
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4b5888b176
Add an attempt at an edge-triggered D flip-flop, using an inverter and
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16 gadi atpakaļ |
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dtflop-ms2.asc
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71b63dac86
Label all nodes meaningfully as possible.
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16 gadi atpakaļ |
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dtflop-ms2.asy
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998662b26f
Rename dtflop-et-ms to dtflop-ms2, everywhere.
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16 gadi atpakaļ |
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dtflop-ms2_test.asc
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650c5bfbb8
Export dtflop-ms2_test to SPICE netlist, with better node names.
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16 gadi atpakaļ |
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dtflop-ms2_test.plt
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998662b26f
Rename dtflop-et-ms to dtflop-ms2, everywhere.
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16 gadi atpakaļ |
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dtflop-msmo.asc
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07d9594910
Rename dtflop-ms to dtflop-msmo (for Mouftah), since it has drawbacks.
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16 gadi atpakaļ |
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dtflop-msmo.asy
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07d9594910
Rename dtflop-ms to dtflop-msmo (for Mouftah), since it has drawbacks.
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16 gadi atpakaļ |
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dtflop-msmo_test.asc
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ad1756634f
In dtflop-msmo_test, show how dtflop-msmo and dtflop-ms2 differ.
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16 gadi atpakaļ |
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dtflop-msmo_test.plt
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ad1756634f
In dtflop-msmo_test, show how dtflop-msmo and dtflop-ms2 differ.
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16 gadi atpakaļ |
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dtflop.asc
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71b63dac86
Label all nodes meaningfully as possible.
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16 gadi atpakaļ |
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dtflop.asy
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bb70144d49
Center all <InstName> attributes on the symbols.
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16 gadi atpakaļ |
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dtflop2.asc
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70fba43cc3
Add synchronous inputs to dtflop2, an experimental D-type tri-flop
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16 gadi atpakaļ |
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dtflop2.asy
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70fba43cc3
Add synchronous inputs to dtflop2, an experimental D-type tri-flop
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16 gadi atpakaļ |
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dtflop2_test.asc
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70fba43cc3
Add synchronous inputs to dtflop2, an experimental D-type tri-flop
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16 gadi atpakaļ |
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dtflop2_test.plt
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45a448c109
Add an experimental D-type flip-flop with asynchronous inputs. Not tested.
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16 gadi atpakaļ |
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dtflop_test.asc
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92f42f8e74
Add a power supply to the D-type flip-flop test circuit, and change it to
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16 gadi atpakaļ |
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dtflop_test.plt
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92f42f8e74
Add a power supply to the D-type flip-flop test circuit, and change it to
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16 gadi atpakaļ |
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dtlatch.asc
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71b63dac86
Label all nodes meaningfully as possible.
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16 gadi atpakaļ |
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dtlatch.asy
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bb70144d49
Center all <InstName> attributes on the symbols.
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16 gadi atpakaļ |
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dtlatch_test.asc
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28ef9619ca
Add a ring oscillator, built with 17 simple ternary inverters, that
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16 gadi atpakaļ |
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dtlatch_test.plt
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46ff8bc067
Add saved plot settings for dtflop and dtlatch, so that after simulating,
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16 gadi atpakaļ |
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fd.asc
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597752acff
Restore FD and RD to D model again since it works, update 1/2 + & - plot settings.
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16 gadi atpakaļ |
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fd.asy
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dc2be664ad
Add symbols, subcircuits, and a test circuit for FD and RD Gates.
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16 gadi atpakaļ |
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full_adder.asc
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31b02a7555
Correctly name the 1:3 decoder (was incorrectly named as a 3:1 decoder).
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16 gadi atpakaļ |
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full_adder.asy
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971558aaf5
Add a full-adder, based on the design by Srivastava and Venkatapathy
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16 gadi atpakaļ |
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full_adder_test.asc
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557cc77e90
Name *-test.* to *_test.*, for consistency.
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16 gadi atpakaļ |
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full_adder_test.plt
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557cc77e90
Name *-test.* to *_test.*, for consistency.
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16 gadi atpakaļ |
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half_adder.asc
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0971f08b1e
Use the fd and rd subcircuits in the half-adder, breaking it.
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16 gadi atpakaļ |
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half_adder.asy
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012e129f7f
Rename adder to half_adder.
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16 gadi atpakaļ |
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half_adder_test.asc
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012e129f7f
Rename adder to half_adder.
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16 gadi atpakaļ |
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half_adder_test.plt
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597752acff
Restore FD and RD to D model again since it works, update 1/2 + & - plot settings.
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16 gadi atpakaļ |
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half_subtractor.asc
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3ab16959f2
Add a half-working half-subtractor.
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16 gadi atpakaļ |
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half_subtractor.asy
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3ab16959f2
Add a half-working half-subtractor.
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16 gadi atpakaļ |
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half_subtractor_test.asc
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3ab16959f2
Add a half-working half-subtractor.
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16 gadi atpakaļ |
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half_subtractor_test.plt
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597752acff
Restore FD and RD to D model again since it works, update 1/2 + & - plot settings.
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16 gadi atpakaļ |
|
input_n.txt
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733954ace9
Change the remaining circuits from microsecond to nanoscale time scale,
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16 gadi atpakaļ |
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input_p.txt
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733954ace9
Change the remaining circuits from microsecond to nanoscale time scale,
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16 gadi atpakaļ |
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input_z.txt
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733954ace9
Change the remaining circuits from microsecond to nanoscale time scale,
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16 gadi atpakaļ |
|
inverter_instance.asc
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22d54879f8
Add instances of cycle_up, decoder, inverter, and min used for logic board creation.
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16 gadi atpakaļ |
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logic_board.asc
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d616e5a932
Logic board: add 4 buffers (need 3 for ALU), and remove 3 tinv's to save space.
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16 gadi atpakaļ |
|
main.asc
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3f171c1e01
Move the inverter out of the clock generator (both versions) and into main.
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16 gadi atpakaļ |
|
main.plt
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3f171c1e01
Move the inverter out of the clock generator (both versions) and into main.
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16 gadi atpakaļ |
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main_cmptest.asc
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74ee971842
Add main architecture with cmptest instruction.
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16 gadi atpakaļ |
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main_cmptest.plt
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74ee971842
Add main architecture with cmptest instruction.
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16 gadi atpakaļ |
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main_jmptest.asc
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376ea0d90d
Split main to main-jmptest, and add swrom-jmptest.
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16 gadi atpakaļ |
|
main_jmptest.plt
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376ea0d90d
Split main to main-jmptest, and add swrom-jmptest.
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16 gadi atpakaļ |
|
main_lwitest.asc
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ea1ae44eb0
TCA0 (main_lwitest): replace with latest TCA2 architecture, but without BE and CMP.
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16 gadi atpakaļ |
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main_lwitest.plt
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ea1ae44eb0
TCA0 (main_lwitest): replace with latest TCA2 architecture, but without BE and CMP.
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16 gadi atpakaļ |
|
max.asc
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71b63dac86
Label all nodes meaningfully as possible.
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16 gadi atpakaļ |
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max.asy
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516ea2a9b9
Add "3" to symbol dyadic gates, so it is clearer that they are trinary.
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16 gadi atpakaļ |
|
min.asc
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71b63dac86
Label all nodes meaningfully as possible.
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16 gadi atpakaļ |
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min.asy
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516ea2a9b9
Add "3" to symbol dyadic gates, so it is clearer that they are trinary.
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16 gadi atpakaļ |
|
min_instance.asc
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22d54879f8
Add instances of cycle_up, decoder, inverter, and min used for logic board creation.
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16 gadi atpakaļ |
|
mux3-1.asc
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31b02a7555
Correctly name the 1:3 decoder (was incorrectly named as a 3:1 decoder).
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16 gadi atpakaļ |
|
mux3-1.asy
|
ef789bccc2
In the 3:1 mux, move the S input within the symbol.
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16 gadi atpakaļ |
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mux3-1_test.asc
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b0a37135fd
Changed name of power supplies in mux3-1_test.asc
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16 gadi atpakaļ |
|
mux3-1_test.plt
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a925a08992
Save plot settings for 3:1 mux.
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16 gadi atpakaļ |
|
mux9-3.asc
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873fda810b
Add notes about more efficient implementations of 1:3 decoder and 9:3 mux.
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16 gadi atpakaļ |
|
mux9-3.asy
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06feb8e046
Add swrom (untested).
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16 gadi atpakaļ |
|
nti.asc
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6947b90592
Improve reference designator names for dtflop-ms and
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16 gadi atpakaļ |
|
nti.asy
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bb70144d49
Center all <InstName> attributes on the symbols.
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16 gadi atpakaļ |
|
pti.asc
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6947b90592
Improve reference designator names for dtflop-ms and
|
16 gadi atpakaļ |
|
pti.asy
|
bb70144d49
Center all <InstName> attributes on the symbols.
|
16 gadi atpakaļ |
|
pznflop.asc
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71b63dac86
Label all nodes meaningfully as possible.
|
16 gadi atpakaļ |
|
pznflop.asy
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7895ecef8d
PZN tri-flop, untested (second try).
|
16 gadi atpakaļ |
|
pznflop_test.asc
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057f8ef746
Demonstrate that pznflop (clocked) functions correctly, now that tnand3 is fixed.
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16 gadi atpakaļ |
|
pznflop_test.plt
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057f8ef746
Demonstrate that pznflop (clocked) functions correctly, now that tnand3 is fixed.
|
16 gadi atpakaļ |
|
pznlatch.asc
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53434f58d9
In the latches and flip-flop, use diagonal wires for the cross-coupled
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16 gadi atpakaļ |
|
pznlatch.asy
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61fe926297
Add clocked PZN flip-flop, untested.
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16 gadi atpakaļ |
|
pznlatch_test.asc
|
f03b5e831a
Rename pznflop to pznlatch, because one common convention now dictates that
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16 gadi atpakaļ |
|
pznlatch_test.plt
|
f03b5e831a
Rename pznflop to pznlatch, because one common convention now dictates that
|
16 gadi atpakaļ |
|
rd.asc
|
597752acff
Restore FD and RD to D model again since it works, update 1/2 + & - plot settings.
|
16 gadi atpakaļ |
|
rd.asy
|
dc2be664ad
Add symbols, subcircuits, and a test circuit for FD and RD Gates.
|
16 gadi atpakaļ |
|
ring_oscillator.asc
|
093a58aeba
Remove a spurious net label.
|
16 gadi atpakaļ |
|
ring_oscillator.plt
|
6e6a66c88b
Make a ring oscillator with a TNAND gate to initialize it. Original
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16 gadi atpakaļ |
|
ring_oscillator_with_ic.asc
|
6e6a66c88b
Make a ring oscillator with a TNAND gate to initialize it. Original
|
16 gadi atpakaļ |
|
shift_down.asc
|
989124e47e
Add shift down gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates.
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16 gadi atpakaļ |
|
shift_down.asy
|
989124e47e
Add shift down gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates.
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16 gadi atpakaļ |
|
shift_test.asc
|
989124e47e
Add shift down gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates.
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16 gadi atpakaļ |
|
shift_test.plt
|
989124e47e
Add shift down gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates.
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16 gadi atpakaļ |
|
shift_up.asc
|
989124e47e
Add shift down gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates. gate, implemented using Mouftah's unary gates.
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16 gadi atpakaļ |
|
shift_up.asy
|
d80e93413b
Add a shift up gate built using Mouftah's gates (untested).
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16 gadi atpakaļ |
|
sp3t-1.asc
|
d002756e2c
Make trit-X files for i,0,1; which look like switches set to either i, 0, or 1.
|
16 gadi atpakaļ |
|
sp3t-1.asy
|
f41deba04b
Reorder SP3T models pin tables to match the NKK SS14M SP3T switches.
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16 gadi atpakaļ |
|
sp3t-2.asc
|
695ef87e1c
Fix sp3t-2, so that trit_test correctly simulates and finds the operating points.
|
16 gadi atpakaļ |
|
sp3t-2.asy
|
f41deba04b
Reorder SP3T models pin tables to match the NKK SS14M SP3T switches.
|
16 gadi atpakaļ |
|
sp3t-3.asc
|
d002756e2c
Make trit-X files for i,0,1; which look like switches set to either i, 0, or 1.
|
16 gadi atpakaļ |
|
sp3t-3.asy
|
f41deba04b
Reorder SP3T models pin tables to match the NKK SS14M SP3T switches.
|
16 gadi atpakaļ |
|
sp3t_test.asc
|
d002756e2c
Make trit-X files for i,0,1; which look like switches set to either i, 0, or 1.
|
16 gadi atpakaļ |
|
sti.asc
|
71b63dac86
Label all nodes meaningfully as possible.
|
16 gadi atpakaļ |
|
sti.asy
|
bb70144d49
Center all <InstName> attributes on the symbols.
|
16 gadi atpakaļ |
|
swrom-blank.asc
|
707e1376d2
Replace sp3t with trit-0 in swrom-blank. New models.
|
16 gadi atpakaļ |
|
swrom-cmptest.asc
|
47ba6e4f70
Add cmptest, to test the CMP instruction.
|
16 gadi atpakaļ |
|
swrom-cmptest.asy
|
47ba6e4f70
Add cmptest, to test the CMP instruction.
|
16 gadi atpakaļ |
|
swrom-fast.asc
|
6079843376
Change swrom-fast symbol to use i, 0, and 1 instead of 0, 1, 2,
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16 gadi atpakaļ |
|
swrom-fast.asy
|
e4b28cbfee
Add symbol and test for behavorial model of 3x3 SWROM with guess.t loaded.
|
16 gadi atpakaļ |
|
swrom-fast_test.asc
|
ffe64e5f80
Change swrom-fast to accept a program given on the top-level
|
16 gadi atpakaļ |
|
swrom-fast_test.plt
|
e4b28cbfee
Add symbol and test for behavorial model of 3x3 SWROM with guess.t loaded.
|
16 gadi atpakaļ |
|
swrom-guess.asc
|
4acda26f9c
Add swrom loaded with guess.t.
|
16 gadi atpakaļ |
|
swrom-guess.asy
|
4acda26f9c
Add swrom loaded with guess.t.
|
16 gadi atpakaļ |
|
swrom-jmptest.asc
|
376ea0d90d
Split main to main-jmptest, and add swrom-jmptest.
|
16 gadi atpakaļ |
|
swrom-jmptest.asy
|
376ea0d90d
Split main to main-jmptest, and add swrom-jmptest.
|
16 gadi atpakaļ |
|
swrom-lwitest.asc
|
12af1d5bce
Add swrom-lwitest, a switch-ROM with lwitest.3 loaded, and
|
16 gadi atpakaļ |
|
swrom-lwitest.asy
|
12af1d5bce
Add swrom-lwitest, a switch-ROM with lwitest.3 loaded, and
|
16 gadi atpakaļ |
|
swrom.asc
|
376ea0d90d
Split main to main-jmptest, and add swrom-jmptest.
|
16 gadi atpakaļ |
|
swrom.asy
|
9fc48c519a
Change switch-ROM bits (from asm/guess.t assembled) to use $G_Vss and $G_Vdd,
|
16 gadi atpakaļ |
|
swrom_test.asc
|
9fc48c519a
Change switch-ROM bits (from asm/guess.t assembled) to use $G_Vss and $G_Vdd,
|
16 gadi atpakaļ |
|
swrom_test.plt
|
78486c24b1
Clean up: remove Draft2 circuit, add v(address) to swrom_test.plt.
|
16 gadi atpakaļ |
|
tbuf.asc
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1c0cd268e8
Add a new tbuf subcircuit, two simple ternary inverters.
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16 gadi atpakaļ |
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tbuf.asy
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1c0cd268e8
Add a new tbuf subcircuit, two simple ternary inverters.
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16 gadi atpakaļ |
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tcycle_down.asc
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71b63dac86
Label all nodes meaningfully as possible.
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16 gadi atpakaļ |
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tcycle_down.asy
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bb70144d49
Center all <InstName> attributes on the symbols.
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16 gadi atpakaļ |
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tcycle_test.asc
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71b63dac86
Label all nodes meaningfully as possible.
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16 gadi atpakaļ |
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tcycle_test.plt
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6bace237a7
Add cycle up gate, and add it to the tcycle_test test circuit.
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16 gadi atpakaļ |
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tcycle_up.asc
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71b63dac86
Label all nodes meaningfully as possible.
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16 gadi atpakaļ |
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tcycle_up.asy
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bb70144d49
Center all <InstName> attributes on the symbols.
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16 gadi atpakaļ |
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tg.asc
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6947b90592
Improve reference designator names for dtflop-ms and
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16 gadi atpakaļ |
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tg.asy
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bb70144d49
Center all <InstName> attributes on the symbols.
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16 gadi atpakaļ |
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tg_test.asc
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ce05b26851
Add a working 3:1 multiplexer of custom design, using CMOS t-gates.
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16 gadi atpakaļ |
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tg_test.plt
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1f8779e9f7
Test the transmission gate (and it works).
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16 gadi atpakaļ |
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tinv.asc
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6d672e75f9
Changed 10k to 12k pull-middle resistors in all gates.
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16 gadi atpakaļ |
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tinv.asy
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bb70144d49
Center all <InstName> attributes on the symbols.
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16 gadi atpakaļ |
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tinv_test.asc
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f0376bfa82
Use better node and part names.
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16 gadi atpakaļ |
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tinv_test.plt
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733954ace9
Change the remaining circuits from microsecond to nanoscale time scale,
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16 gadi atpakaļ |
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tnand.asc
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3ed865b929
Support translating the 'tnand' subcircuit using bb.py.
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16 gadi atpakaļ |
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tnand.asy
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516ea2a9b9
Add "3" to symbol dyadic gates, so it is clearer that they are trinary.
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16 gadi atpakaļ |
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tnand3.asc
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71b63dac86
Label all nodes meaningfully as possible.
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16 gadi atpakaļ |
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tnand3.asy
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bb70144d49
Center all <InstName> attributes on the symbols.
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16 gadi atpakaļ |
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tnand_test.asc
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7d6aff9338
Add MAX gate (inverted TNOR), untested.
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16 gadi atpakaļ |
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tnand_test.plt
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733954ace9
Change the remaining circuits from microsecond to nanoscale time scale,
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16 gadi atpakaļ |
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tnor.asc
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cf170ccdf2
In tnor, label all nodes usefully.
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16 gadi atpakaļ |
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tnor.asy
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516ea2a9b9
Add "3" to symbol dyadic gates, so it is clearer that they are trinary.
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16 gadi atpakaļ |
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tnor3.asc
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71b63dac86
Label all nodes meaningfully as possible.
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16 gadi atpakaļ |
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tnor3.asy
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bb70144d49
Center all <InstName> attributes on the symbols.
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16 gadi atpakaļ |
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tnor3_test.asc
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71b63dac86
Label all nodes meaningfully as possible.
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16 gadi atpakaļ |
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tnor3_test.plt
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733954ace9
Change the remaining circuits from microsecond to nanoscale time scale,
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16 gadi atpakaļ |
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tnor_test.asc
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7d6aff9338
Add MAX gate (inverted TNOR), untested.
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16 gadi atpakaļ |
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tnor_test.plt
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733954ace9
Change the remaining circuits from microsecond to nanoscale time scale,
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16 gadi atpakaļ |
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tpower.asc
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028cd72fb4
Add LTSpice circuits and symbols for D-type latch, PZN tri-flop,
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16 gadi atpakaļ |
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tpower.asy
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028cd72fb4
Add LTSpice circuits and symbols for D-type latch, PZN tri-flop,
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16 gadi atpakaļ |
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tpower_test.asc
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21b41aea34
Connect PMOS and NMOS bodies to Vdd and Vss, so the body effect will be taken
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16 gadi atpakaļ |
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trit-0.asc
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c9971298c3
Name sp3t-{1,2,3} subcircuits in trit-{i,0,1} as sw_{i,0,1}, to easily distinguish.
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16 gadi atpakaļ |
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trit-0.asy
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d002756e2c
Make trit-X files for i,0,1; which look like switches set to either i, 0, or 1.
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16 gadi atpakaļ |
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trit-1.asc
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c9971298c3
Name sp3t-{1,2,3} subcircuits in trit-{i,0,1} as sw_{i,0,1}, to easily distinguish.
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16 gadi atpakaļ |
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trit-1.asy
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d002756e2c
Make trit-X files for i,0,1; which look like switches set to either i, 0, or 1.
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16 gadi atpakaļ |
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trit-i.asc
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c9971298c3
Name sp3t-{1,2,3} subcircuits in trit-{i,0,1} as sw_{i,0,1}, to easily distinguish.
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16 gadi atpakaļ |
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trit-i.asy
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d002756e2c
Make trit-X files for i,0,1; which look like switches set to either i, 0, or 1.
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16 gadi atpakaļ |
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trit_reg3.asc
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ad1756634f
In dtflop-msmo_test, show how dtflop-msmo and dtflop-ms2 differ.
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16 gadi atpakaļ |
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trit_reg3.asy
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f54c7ee726
Change trit_reg3 (and therefore main) to use dtflop_ms, instead of dtflop_ms2.
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16 gadi atpakaļ |
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trit_reg3_test.asc
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ad1756634f
In dtflop-msmo_test, show how dtflop-msmo and dtflop-ms2 differ.
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16 gadi atpakaļ |
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trit_reg3_test.plt
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b4e92805c2
Annonate the trit_reg3_test graph, which doesn't match http://jeff.tk/wiki/Image:3-Trit_Register_Timing_Diagram.png.
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16 gadi atpakaļ |
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trit_test.asc
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695ef87e1c
Fix sp3t-2, so that trit_test correctly simulates and finds the operating points.
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16 gadi atpakaļ |
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tsign3.asc
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3e7c242041
Add 4-trit sign detector, rename 3-trit one to tsign3.
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16 gadi atpakaļ |
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tsign3.asy
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3e7c242041
Add 4-trit sign detector, rename 3-trit one to tsign3.
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16 gadi atpakaļ |
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tsign4.asc
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3e7c242041
Add 4-trit sign detector, rename 3-trit one to tsign3.
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16 gadi atpakaļ |
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tsign4.asy
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3e7c242041
Add 4-trit sign detector, rename 3-trit one to tsign3.
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16 gadi atpakaļ |
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tsign_test.asc
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149605f08a
Sign detector board: use resistor network (PCB not laid out).
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16 gadi atpakaļ |
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tsign_test.plt
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9a65ad934c
tsign_test: only test 4-trit sign detector.
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16 gadi atpakaļ |
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ttlatch.asc
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71b63dac86
Label all nodes meaningfully as possible.
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16 gadi atpakaļ |
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ttlatch.asy
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f6fbb1ff28
Add T-type tri-latch with PZN inputs (untested).
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16 gadi atpakaļ |
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ttlatch_test.asc
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a41b2905f7
Fix ttlatch, one of the inputs to a TNOR3 was miswired.
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16 gadi atpakaļ |
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ttlatch_test.plt
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253ebea37d
At least the P, Z, and N inputs of ttlatch appear to work, when T=i. Have not
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16 gadi atpakaļ |
Jeff Connelly
d46c59be12
Shorten simulation time by 5/2 for clock_gen_test.