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Грана: orangecrab_backport
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microwatt-mi...
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Tobias Platen 72ae258962 inital support for orangecrab0.2 пре 2 година
.github 93b2987b19 ci: use job.container пре 3 година
constraints 9a967e764b found chiselwatt ulx3s constraint file пре 2 година
fpga 72ae258962 inital support for orangecrab0.2 пре 2 година
hello_world bc4e6b7efe Reduce hello_world footprint to fit in 8kB пре 3 година
include 9b5bd2d757 rrright. ok. these modifications to sdram_init allow it пре 2 година
lib d654667304 console: Add support for the 16550 UART пре 3 година
litedram d58b112a12 add EXTRA_CFLAGS to CFLAGS пре 2 година
liteeth 8366710217 liteeth: Hook up LiteX LiteEth ethernet controller пре 3 година
media 0cb0f78777 Add title image пре 4 година
micropython 434962bc34 tests: Add updated micropython build with 16550 support пре 3 година
openocd d92624f9c0 add ulx3s openocd config for ft232 пре 2 година
rust_lib_demo e3941109af console: Cleanup console API пре 3 година
scripts 89a67a18d0 decode: Add a facility field to the instruction decode tables пре 3 година
sim-unisim ee52fd4d80 Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs пре 4 година
tests 81b96e024e add first cut of ulx3s constraint file пре 2 година
uart16550 aae45583d7 Add uart16550 files from fusesoc пре 3 година
verilator 81b96e024e add first cut of ulx3s constraint file пре 2 година
.gitignore 3460afb557 Add yosys builds files to gitignore пре 3 година
LICENSE 5a29cb4699 Initial import of microwatt пре 4 година
Makefile 72ae258962 inital support for orangecrab0.2 пре 2 година
README.md 6326efaca4 Add Makefile command line variables to enable docker and podman пре 4 година
cache_ram.vhdl ecaa5e2fb2 dcache: Rework RAM wrapper to synthetize better on Xilinx пре 4 година
common.vhdl f636bb7c39 dcache: Fix bugs in pipelined operation пре 3 година
control.vhdl 3cd3449b4b core: Move redirect and interrupt delivery logic to writeback пре 3 година
core.vhdl 1610e1fa21 add verilator snoop of LDST request address пре 2 година
core_debug.vhdl 3361c460b8 core_debug: Stop logging 256 cycles after trigger пре 3 година
core_dram_tb.vhdl 02abb135a8 litedram: l2: Add support for more geometries пре 3 година
core_dummy.vhdl 1610e1fa21 add verilator snoop of LDST request address пре 2 година
core_flash_tb.vhdl bf7def5503 soc: Don't require dram wishbones signals to be wired by toplevel пре 4 година
core_tb.vhdl bf7def5503 soc: Don't require dram wishbones signals to be wired by toplevel пре 4 година
countzero.vhdl 9d285a265c core: Add support for single-precision FP loads and stores пре 3 година
countzero_tb.vhdl ab86b58d95 Exit cleanly from testbench on success пре 4 година
cr_file.vhdl 893d2bc6a2 core: Don't generate logic for log data when LOG_LENGTH = 0 пре 3 година
crhelpers.vhdl da0bd89c43 crhelpers: Constraint "crnum" integer пре 4 година
dcache.vhdl f636bb7c39 dcache: Fix bugs in pipelined operation пре 3 година
dcache_tb.vhdl ab86b58d95 Exit cleanly from testbench on success пре 4 година
decode1.vhdl ae2afeca5c core: Track CR hazards and bypasses using tags пре 3 година
decode2.vhdl 4fd8d9509c execute1: Move CR result to data path process пре 3 година
decode_types.vhdl 4c61a71a62 core: Crack update-form loads into two internal ops пре 3 година
divider.vhdl c9a2076dd3 execute1: Remember dest GPR, RC, OE, XER for slow operations пре 4 година
divider_tb.vhdl ab86b58d95 Exit cleanly from testbench on success пре 4 година
dmi_dtm_dummy.vhdl 8102e7863b Fix build issue in dmi_dtm_dummy.vhdl пре 4 година
dmi_dtm_ecp5.vhdl 72ae258962 inital support for orangecrab0.2 пре 2 година
dmi_dtm_tb.vhdl 8e0389b973 ram: Rework main RAM interface пре 4 година
dmi_dtm_xilinx.vhdl 5eb351b4be Reset JTAG/DMI пре 3 година
dram_tb.vhdl 02abb135a8 litedram: l2: Add support for more geometries пре 3 година
execute1.vhdl acb3d2d745 core: Send FPU interrupts to writeback rather than execute1 пре 3 година
fetch1.vhdl 3cd3449b4b core: Move redirect and interrupt delivery logic to writeback пре 3 година
fpu.vhdl acb3d2d745 core: Send FPU interrupts to writeback rather than execute1 пре 3 година
glibc_random.vhdl 06392e7eaa Reformat glibc_random пре 4 година
glibc_random_helpers.vhdl 06392e7eaa Reformat glibc_random пре 4 година
helpers.vhdl 9d285a265c core: Add support for single-precision FP loads and stores пре 3 година
icache.vhdl 0fb207be60 fetch1: Implement a simple branch target cache пре 3 година
icache_tb.vhdl b5a7dbb78d core: Remove fetch2 pipeline stage пре 4 година
icache_test.bin f74e8a4f79 icache_tb: Improve test and include test file пре 4 година
insn_helpers.vhdl 4b2c23703c core: Implement quadword loads and stores пре 3 година
loadstore1.vhdl f636bb7c39 dcache: Fix bugs in pipelined operation пре 3 година
logical.vhdl 658feabfd4 core: Make result multiplexing explicit пре 3 година
microwatt.core ae2afeca5c core: Track CR hazards and bypasses using tags пре 3 година
mmu.vhdl 740f013284 Initialize PID register пре 3 година
multiply.vhdl f1238299bd execute1: Take an extra cycle for OE=1 multiply instructions пре 3 година
multiply_tb.vhdl 535341961d multiplier: Generalize interface to the multiplier пре 3 година
nonrandom.vhdl 1a7aebeef8 Add random number generator and implement the darn instruction пре 3 година
plru.vhdl e598188aca plru: Improve sensitivity list пре 4 година
plru_tb.vhdl ab86b58d95 Exit cleanly from testbench on success пре 4 година
ppc_fx_insns.vhdl 8edfbf638b core: Implement the cmpeqb and cmprb instructions пре 3 година
random.vhdl 1a7aebeef8 Add random number generator and implement the darn instruction пре 3 година
register_file.vhdl 45cd8f4fc3 core: Add support for floating-point loads and stores пре 3 година
rotator.vhdl 8a0a907e2f Implement the extswsli instruction пре 4 година
rotator_tb.vhdl ab86b58d95 Exit cleanly from testbench on success пре 4 година
sim_16550_uart.vhdl cc10f6b289 uart: Add a simulation model for the 16550 compatible UART пре 3 година
sim_bram.vhdl 8e0389b973 ram: Rework main RAM interface пре 4 година
sim_bram_helpers.vhdl 8e0389b973 ram: Rework main RAM interface пре 4 година
sim_bram_helpers_c.c 471c7e2197 Consolidate VHPI code пре 4 година
sim_console.vhdl fd9e971b2c Reformat sim_console пре 4 година
sim_console_c.c fc4e13ae67 sim_console: Fix polling to check for POLLIN пре 3 година
sim_jtag.vhdl 554b753172 Add jtag support in simulation via a socket пре 4 година
sim_jtag_socket.vhdl 554b753172 Add jtag support in simulation via a socket пре 4 година
sim_jtag_socket_c.c 471c7e2197 Consolidate VHPI code пре 4 година
sim_no_flash.vhdl a89e1469ef spi: Add simulation support пре 4 година
sim_pp_uart.vhdl 4eae29801b uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl пре 3 година
sim_vhpi_c.c 471c7e2197 Consolidate VHPI code пре 4 година
sim_vhpi_c.h 471c7e2197 Consolidate VHPI code пре 4 година
soc.vhdl 79461a96bd link unused signals to undefined пре 2 година
spi_flash_ctrl.vhdl c870040a20 Fix an issue in flash controller when BOOT_CLOCKS is false пре 3 година
spi_rxtx.vhdl 3f1e2b3a4f Merge pull request #265 from antonblanchard/another-spi-rxtx-reset-issu пре 3 година
sync_fifo.vhdl a3857aac94 litedram: Add an L2 cache with store queue пре 4 година
syscon.vhdl 6431824a5f add SIM_BRAM_CHAINBOOT parameter to SYSCON пре 2 година
utils.vhdl bf1b98b958 litedram: Add support for booting without BRAM пре 4 година
wishbone_arbiter.vhdl cff4b13a9b wb_arbiter: Early master selection пре 4 година
wishbone_bram_tb.bin 8e0389b973 ram: Rework main RAM interface пре 4 година
wishbone_bram_tb.vhdl ab86b58d95 Exit cleanly from testbench on success пре 4 година
wishbone_bram_wrapper.vhdl 2260ca654d gotten over the logic-dyslexia of what in/out mean in VHDL. пре 2 година
wishbone_debug_master.vhdl fe789190e4 wishbone_debug_master: Fix address auto-increment for memory writes пре 4 година
wishbone_types.vhdl c6dfc19d89 Make wishbone_master_out and wb_io_master_out match пре 3 година
writeback.vhdl acb3d2d745 core: Send FPU interrupts to writeback rather than execute1 пре 3 година
xics.vhdl bb54af59de xics: Add support for reduced priority field size пре 3 година
xilinx-mult.vhdl f1238299bd execute1: Take an extra cycle for OE=1 multiply instructions пре 3 година

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)