wbsio_spi.c 6.1 KB

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  1. /*
  2. * This file is part of the flashrom project.
  3. *
  4. * Copyright (C) 2008 Peter Stuge <peter@stuge.se>
  5. * Copyright (C) 2009,2010 Carl-Daniel Hailfinger
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. */
  20. #if defined(__i386__) || defined(__x86_64__)
  21. #include "flash.h"
  22. #include "chipdrivers.h"
  23. #include "programmer.h"
  24. #include "hwaccess.h"
  25. #include "spi.h"
  26. #define WBSIO_PORT1 0x2e
  27. #define WBSIO_PORT2 0x4e
  28. static uint16_t wbsio_spibase = 0;
  29. static uint16_t wbsio_get_spibase(uint16_t port)
  30. {
  31. uint8_t id;
  32. uint16_t flashport = 0;
  33. w836xx_ext_enter(port);
  34. id = sio_read(port, 0x20);
  35. if (id != 0xa0) {
  36. msg_perr("\nW83627 not found at 0x%x, id=0x%02x want=0xa0.\n", port, id);
  37. goto done;
  38. }
  39. if (0 == (sio_read(port, 0x24) & 2)) {
  40. msg_perr("\nW83627 found at 0x%x, but SPI pins are not enabled. (CR[0x24] bit 1=0)\n", port);
  41. goto done;
  42. }
  43. sio_write(port, 0x07, 0x06);
  44. if (0 == (sio_read(port, 0x30) & 1)) {
  45. msg_perr("\nW83627 found at 0x%x, but SPI is not enabled. (LDN6[0x30] bit 0=0)\n", port);
  46. goto done;
  47. }
  48. flashport = (sio_read(port, 0x62) << 8) | sio_read(port, 0x63);
  49. done:
  50. w836xx_ext_leave(port);
  51. return flashport;
  52. }
  53. static int wbsio_spi_send_command(struct flashctx *flash, unsigned int writecnt,
  54. unsigned int readcnt,
  55. const unsigned char *writearr,
  56. unsigned char *readarr);
  57. static int wbsio_spi_read(struct flashctx *flash, uint8_t *buf,
  58. unsigned int start, unsigned int len);
  59. static const struct spi_master spi_master_wbsio = {
  60. .type = SPI_CONTROLLER_WBSIO,
  61. .max_data_read = MAX_DATA_UNSPECIFIED,
  62. .max_data_write = MAX_DATA_UNSPECIFIED,
  63. .command = wbsio_spi_send_command,
  64. .multicommand = default_spi_send_multicommand,
  65. .read = wbsio_spi_read,
  66. .write_256 = spi_chip_write_1,
  67. .write_aai = default_spi_write_aai,
  68. };
  69. int wbsio_check_for_spi(void)
  70. {
  71. if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1)))
  72. if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT2)))
  73. return 1;
  74. msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase);
  75. msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is "
  76. "1024 kB!\n", __func__);
  77. max_rom_decode.spi = 1024 * 1024;
  78. register_spi_master(&spi_master_wbsio);
  79. return 0;
  80. }
  81. /* W83627DHG has 11 command modes:
  82. * 1=1 command only
  83. * 2=1 command+1 data write
  84. * 3=1 command+2 data read
  85. * 4=1 command+3 address
  86. * 5=1 command+3 address+1 data write
  87. * 6=1 command+3 address+4 data write
  88. * 7=1 command+3 address+1 dummy address inserted by wbsio+4 data read
  89. * 8=1 command+3 address+1 data read
  90. * 9=1 command+3 address+2 data read
  91. * a=1 command+3 address+3 data read
  92. * b=1 command+3 address+4 data read
  93. *
  94. * mode[7:4] holds the command mode
  95. * mode[3:0] holds SPI address bits [19:16]
  96. *
  97. * The Winbond SPI master only supports 20 bit addresses on the SPI bus. :\
  98. * Would one more byte of RAM in the chip (to get all 24 bits) really make
  99. * such a big difference?
  100. */
  101. static int wbsio_spi_send_command(struct flashctx *flash, unsigned int writecnt,
  102. unsigned int readcnt,
  103. const unsigned char *writearr,
  104. unsigned char *readarr)
  105. {
  106. int i;
  107. uint8_t mode = 0;
  108. msg_pspew("%s:", __func__);
  109. if (1 == writecnt && 0 == readcnt) {
  110. mode = 0x10;
  111. } else if (2 == writecnt && 0 == readcnt) {
  112. OUTB(writearr[1], wbsio_spibase + 4);
  113. msg_pspew(" data=0x%02x", writearr[1]);
  114. mode = 0x20;
  115. } else if (1 == writecnt && 2 == readcnt) {
  116. mode = 0x30;
  117. } else if (4 == writecnt && 0 == readcnt) {
  118. msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f));
  119. for (i = 2; i < writecnt; i++) {
  120. OUTB(writearr[i], wbsio_spibase + i);
  121. msg_pspew("%02x", writearr[i]);
  122. }
  123. mode = 0x40 | (writearr[1] & 0x0f);
  124. } else if (5 == writecnt && 0 == readcnt) {
  125. msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f));
  126. for (i = 2; i < 4; i++) {
  127. OUTB(writearr[i], wbsio_spibase + i);
  128. msg_pspew("%02x", writearr[i]);
  129. }
  130. OUTB(writearr[i], wbsio_spibase + i);
  131. msg_pspew(" data=0x%02x", writearr[i]);
  132. mode = 0x50 | (writearr[1] & 0x0f);
  133. } else if (8 == writecnt && 0 == readcnt) {
  134. msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f));
  135. for (i = 2; i < 4; i++) {
  136. OUTB(writearr[i], wbsio_spibase + i);
  137. msg_pspew("%02x", writearr[i]);
  138. }
  139. msg_pspew(" data=0x");
  140. for (; i < writecnt; i++) {
  141. OUTB(writearr[i], wbsio_spibase + i);
  142. msg_pspew("%02x", writearr[i]);
  143. }
  144. mode = 0x60 | (writearr[1] & 0x0f);
  145. } else if (5 == writecnt && 4 == readcnt) {
  146. /* XXX: TODO not supported by flashrom infrastructure!
  147. * This mode, 7, discards the fifth byte in writecnt,
  148. * but since we can not express that in flashrom, fail
  149. * the operation for now.
  150. */
  151. ;
  152. } else if (4 == writecnt && readcnt >= 1 && readcnt <= 4) {
  153. msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f));
  154. for (i = 2; i < writecnt; i++) {
  155. OUTB(writearr[i], wbsio_spibase + i);
  156. msg_pspew("%02x", writearr[i]);
  157. }
  158. mode = ((7 + readcnt) << 4) | (writearr[1] & 0x0f);
  159. }
  160. msg_pspew(" cmd=%02x mode=%02x\n", writearr[0], mode);
  161. if (!mode) {
  162. msg_perr("%s: unsupported command type wr=%d rd=%d\n",
  163. __func__, writecnt, readcnt);
  164. /* Command type refers to the number of bytes read/written. */
  165. return SPI_INVALID_LENGTH;
  166. }
  167. OUTB(writearr[0], wbsio_spibase);
  168. OUTB(mode, wbsio_spibase + 1);
  169. programmer_delay(10);
  170. if (!readcnt)
  171. return 0;
  172. msg_pspew("%s: returning data =", __func__);
  173. for (i = 0; i < readcnt; i++) {
  174. readarr[i] = INB(wbsio_spibase + 4 + i);
  175. msg_pspew(" 0x%02x", readarr[i]);
  176. }
  177. msg_pspew("\n");
  178. return 0;
  179. }
  180. static int wbsio_spi_read(struct flashctx *flash, uint8_t *buf,
  181. unsigned int start, unsigned int len)
  182. {
  183. mmio_readn((void *)(flash->virtual_memory + start), buf, len);
  184. return 0;
  185. }
  186. #endif