tc-m32r.c 67 KB

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  1. /* tc-m32r.c -- Assembler for the Renesas M32R.
  2. Copyright (C) 1996-2015 Free Software Foundation, Inc.
  3. This file is part of GAS, the GNU Assembler.
  4. GAS is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 3, or (at your option)
  7. any later version.
  8. GAS is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with GAS; see the file COPYING. If not, write to
  14. the Free Software Foundation, 51 Franklin Street - Fifth Floor,
  15. Boston, MA 02110-1301, USA. */
  16. #include "as.h"
  17. #include "safe-ctype.h"
  18. #include "subsegs.h"
  19. #include "symcat.h"
  20. #include "opcodes/m32r-desc.h"
  21. #include "opcodes/m32r-opc.h"
  22. #include "cgen.h"
  23. #include "elf/m32r.h"
  24. /* Linked list of symbols that are debugging symbols to be defined as the
  25. beginning of the current instruction. */
  26. typedef struct sym_link
  27. {
  28. struct sym_link *next;
  29. symbolS *symbol;
  30. } sym_linkS;
  31. static sym_linkS *debug_sym_link = (sym_linkS *) 0;
  32. /* Structure to hold all of the different components describing
  33. an individual instruction. */
  34. typedef struct
  35. {
  36. const CGEN_INSN *insn;
  37. const CGEN_INSN *orig_insn;
  38. CGEN_FIELDS fields;
  39. #if CGEN_INT_INSN_P
  40. CGEN_INSN_INT buffer[1];
  41. #define INSN_VALUE(buf) (*(buf))
  42. #else
  43. unsigned char buffer[CGEN_MAX_INSN_SIZE];
  44. #define INSN_VALUE(buf) (buf)
  45. #endif
  46. char *addr;
  47. fragS *frag;
  48. int num_fixups;
  49. fixS *fixups[GAS_CGEN_MAX_FIXUPS];
  50. int indices[MAX_OPERAND_INSTANCES];
  51. sym_linkS *debug_sym_link;
  52. }
  53. m32r_insn;
  54. /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
  55. boundary (i.e. was the first of two 16 bit insns). */
  56. static m32r_insn prev_insn;
  57. /* Non-zero if we've seen a relaxable insn since the last 32 bit
  58. alignment request. */
  59. static int seen_relaxable_p = 0;
  60. /* Non-zero if we are generating PIC code. */
  61. int pic_code;
  62. /* Non-zero if -relax specified, in which case sufficient relocs are output
  63. for the linker to do relaxing.
  64. We do simple forms of relaxing internally, but they are always done.
  65. This flag does not apply to them. */
  66. static int m32r_relax;
  67. /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
  68. Each high/shigh reloc must be paired with it's low cousin in order to
  69. properly calculate the addend in a relocatable link (since there is a
  70. potential carry from the low to the high/shigh).
  71. This option is off by default though for user-written assembler code it
  72. might make sense to make the default be on (i.e. have gcc pass a flag
  73. to turn it off). This warning must not be on for GCC created code as
  74. optimization may delete the low but not the high/shigh (at least we
  75. shouldn't assume or require it to). */
  76. static int warn_unmatched_high = 0;
  77. /* 1 if -m32rx has been specified, in which case support for
  78. the extended M32RX instruction set should be enabled.
  79. 2 if -m32r2 has been specified, in which case support for
  80. the extended M32R2 instruction set should be enabled. */
  81. static int enable_m32rx = 0; /* Default to M32R. */
  82. /* Non-zero if -m32rx -hidden has been specified, in which case support for
  83. the special M32RX instruction set should be enabled. */
  84. static int enable_special = 0;
  85. /* Non-zero if -bitinst has been specified, in which case support
  86. for extended M32R bit-field instruction set should be enabled. */
  87. static int enable_special_m32r = 1;
  88. /* Non-zero if -float has been specified, in which case support for
  89. extended M32R floating point instruction set should be enabled. */
  90. static int enable_special_float = 0;
  91. /* Non-zero if the programmer should be warned when an explicit parallel
  92. instruction might have constraint violations. */
  93. static int warn_explicit_parallel_conflicts = 1;
  94. /* Non-zero if the programmer should not receive any messages about
  95. parallel instruction with potential or real constraint violations.
  96. The ability to suppress these messages is intended only for hardware
  97. vendors testing the chip. It superceedes
  98. warn_explicit_parallel_conflicts. */
  99. static int ignore_parallel_conflicts = 0;
  100. /* Non-zero if insns can be made parallel. */
  101. static int use_parallel = 0;
  102. /* Non-zero if optimizations should be performed. */
  103. static int optimize;
  104. /* m32r er_flags. */
  105. static int m32r_flags = 0;
  106. /* Stuff for .scomm symbols. */
  107. static segT sbss_section;
  108. static asection scom_section;
  109. static asymbol scom_symbol;
  110. const char comment_chars[] = ";";
  111. const char line_comment_chars[] = "#";
  112. const char line_separator_chars[] = "!";
  113. const char EXP_CHARS[] = "eE";
  114. const char FLT_CHARS[] = "dD";
  115. /* Relocations against symbols are done in two
  116. parts, with a HI relocation and a LO relocation. Each relocation
  117. has only 16 bits of space to store an addend. This means that in
  118. order for the linker to handle carries correctly, it must be able
  119. to locate both the HI and the LO relocation. This means that the
  120. relocations must appear in order in the relocation table.
  121. In order to implement this, we keep track of each unmatched HI
  122. relocation. We then sort them so that they immediately precede the
  123. corresponding LO relocation. */
  124. struct m32r_hi_fixup
  125. {
  126. /* Next HI fixup. */
  127. struct m32r_hi_fixup *next;
  128. /* This fixup. */
  129. fixS *fixp;
  130. /* The section this fixup is in. */
  131. segT seg;
  132. };
  133. /* The list of unmatched HI relocs. */
  134. static struct m32r_hi_fixup *m32r_hi_fixup_list;
  135. struct
  136. {
  137. enum bfd_architecture bfd_mach;
  138. int mach_flags;
  139. } mach_table[] =
  140. {
  141. { bfd_mach_m32r, (1<<MACH_M32R) },
  142. { bfd_mach_m32rx, (1<<MACH_M32RX) },
  143. { bfd_mach_m32r2, (1<<MACH_M32R2) }
  144. };
  145. static void
  146. allow_m32rx (int on)
  147. {
  148. enable_m32rx = on;
  149. if (stdoutput != NULL)
  150. bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_table[on].bfd_mach);
  151. if (gas_cgen_cpu_desc != NULL)
  152. gas_cgen_cpu_desc->machs = mach_table[on].mach_flags;
  153. }
  154. #define M32R_SHORTOPTS "O::K:"
  155. const char *md_shortopts = M32R_SHORTOPTS;
  156. enum md_option_enums
  157. {
  158. OPTION_M32R = OPTION_MD_BASE,
  159. OPTION_M32RX,
  160. OPTION_M32R2,
  161. OPTION_BIG,
  162. OPTION_LITTLE,
  163. OPTION_PARALLEL,
  164. OPTION_NO_PARALLEL,
  165. OPTION_WARN_PARALLEL,
  166. OPTION_NO_WARN_PARALLEL,
  167. OPTION_IGNORE_PARALLEL,
  168. OPTION_NO_IGNORE_PARALLEL,
  169. OPTION_SPECIAL,
  170. OPTION_SPECIAL_M32R,
  171. OPTION_NO_SPECIAL_M32R,
  172. OPTION_SPECIAL_FLOAT,
  173. OPTION_WARN_UNMATCHED,
  174. OPTION_NO_WARN_UNMATCHED
  175. };
  176. struct option md_longopts[] =
  177. {
  178. {"m32r", no_argument, NULL, OPTION_M32R},
  179. {"m32rx", no_argument, NULL, OPTION_M32RX},
  180. {"m32r2", no_argument, NULL, OPTION_M32R2},
  181. {"big", no_argument, NULL, OPTION_BIG},
  182. {"little", no_argument, NULL, OPTION_LITTLE},
  183. {"EB", no_argument, NULL, OPTION_BIG},
  184. {"EL", no_argument, NULL, OPTION_LITTLE},
  185. {"parallel", no_argument, NULL, OPTION_PARALLEL},
  186. {"no-parallel", no_argument, NULL, OPTION_NO_PARALLEL},
  187. {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL},
  188. {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL},
  189. {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
  190. {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
  191. {"ignore-parallel-conflicts", no_argument, NULL, OPTION_IGNORE_PARALLEL},
  192. {"Ip", no_argument, NULL, OPTION_IGNORE_PARALLEL},
  193. {"no-ignore-parallel-conflicts", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL},
  194. {"nIp", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL},
  195. {"hidden", no_argument, NULL, OPTION_SPECIAL},
  196. {"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R},
  197. {"no-bitinst", no_argument, NULL, OPTION_NO_SPECIAL_M32R},
  198. {"float", no_argument, NULL, OPTION_SPECIAL_FLOAT},
  199. /* Sigh. I guess all warnings must now have both variants. */
  200. {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED},
  201. {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED},
  202. {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
  203. {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
  204. {NULL, no_argument, NULL, 0}
  205. };
  206. size_t md_longopts_size = sizeof (md_longopts);
  207. static void
  208. little (int on)
  209. {
  210. target_big_endian = ! on;
  211. }
  212. /* Use parallel execution. */
  213. static int
  214. parallel (void)
  215. {
  216. if (! enable_m32rx)
  217. return 0;
  218. if (use_parallel == 1)
  219. return 1;
  220. return 0;
  221. }
  222. int
  223. md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
  224. {
  225. switch (c)
  226. {
  227. case 'O':
  228. optimize = 1;
  229. use_parallel = 1;
  230. break;
  231. case OPTION_M32R:
  232. allow_m32rx (0);
  233. break;
  234. case OPTION_M32RX:
  235. allow_m32rx (1);
  236. break;
  237. case OPTION_M32R2:
  238. allow_m32rx (2);
  239. enable_special = 1;
  240. enable_special_m32r = 1;
  241. break;
  242. case OPTION_BIG:
  243. target_big_endian = 1;
  244. break;
  245. case OPTION_LITTLE:
  246. target_big_endian = 0;
  247. break;
  248. case OPTION_PARALLEL:
  249. use_parallel = 1;
  250. break;
  251. case OPTION_NO_PARALLEL:
  252. use_parallel = 0;
  253. break;
  254. case OPTION_WARN_PARALLEL:
  255. warn_explicit_parallel_conflicts = 1;
  256. break;
  257. case OPTION_NO_WARN_PARALLEL:
  258. warn_explicit_parallel_conflicts = 0;
  259. break;
  260. case OPTION_IGNORE_PARALLEL:
  261. ignore_parallel_conflicts = 1;
  262. break;
  263. case OPTION_NO_IGNORE_PARALLEL:
  264. ignore_parallel_conflicts = 0;
  265. break;
  266. case OPTION_SPECIAL:
  267. if (enable_m32rx)
  268. enable_special = 1;
  269. else
  270. {
  271. /* Pretend that we do not recognise this option. */
  272. as_bad (_("Unrecognised option: -hidden"));
  273. return 0;
  274. }
  275. break;
  276. case OPTION_SPECIAL_M32R:
  277. enable_special_m32r = 1;
  278. break;
  279. case OPTION_NO_SPECIAL_M32R:
  280. enable_special_m32r = 0;
  281. break;
  282. case OPTION_SPECIAL_FLOAT:
  283. enable_special_float = 1;
  284. break;
  285. case OPTION_WARN_UNMATCHED:
  286. warn_unmatched_high = 1;
  287. break;
  288. case OPTION_NO_WARN_UNMATCHED:
  289. warn_unmatched_high = 0;
  290. break;
  291. case 'K':
  292. if (strcmp (arg, "PIC") != 0)
  293. as_warn (_("Unrecognized option following -K"));
  294. else
  295. pic_code = 1;
  296. break;
  297. default:
  298. return 0;
  299. }
  300. return 1;
  301. }
  302. void
  303. md_show_usage (FILE *stream)
  304. {
  305. fprintf (stream, _(" M32R specific command line options:\n"));
  306. fprintf (stream, _("\
  307. -m32r disable support for the m32rx instruction set\n"));
  308. fprintf (stream, _("\
  309. -m32rx support the extended m32rx instruction set\n"));
  310. fprintf (stream, _("\
  311. -m32r2 support the extended m32r2 instruction set\n"));
  312. fprintf (stream, _("\
  313. -EL,-little produce little endian code and data\n"));
  314. fprintf (stream, _("\
  315. -EB,-big produce big endian code and data\n"));
  316. fprintf (stream, _("\
  317. -parallel try to combine instructions in parallel\n"));
  318. fprintf (stream, _("\
  319. -no-parallel disable -parallel\n"));
  320. fprintf (stream, _("\
  321. -no-bitinst disallow the M32R2's extended bit-field instructions\n"));
  322. fprintf (stream, _("\
  323. -O try to optimize code. Implies -parallel\n"));
  324. fprintf (stream, _("\
  325. -warn-explicit-parallel-conflicts warn when parallel instructions\n"));
  326. fprintf (stream, _("\
  327. might violate contraints\n"));
  328. fprintf (stream, _("\
  329. -no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
  330. fprintf (stream, _("\
  331. instructions might violate contraints\n"));
  332. fprintf (stream, _("\
  333. -Wp synonym for -warn-explicit-parallel-conflicts\n"));
  334. fprintf (stream, _("\
  335. -Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
  336. fprintf (stream, _("\
  337. -ignore-parallel-conflicts do not check parallel instructions\n"));
  338. fprintf (stream, _("\
  339. for constraint violations\n"));
  340. fprintf (stream, _("\
  341. -no-ignore-parallel-conflicts check parallel instructions for\n"));
  342. fprintf (stream, _("\
  343. constraint violations\n"));
  344. fprintf (stream, _("\
  345. -Ip synonym for -ignore-parallel-conflicts\n"));
  346. fprintf (stream, _("\
  347. -nIp synonym for -no-ignore-parallel-conflicts\n"));
  348. fprintf (stream, _("\
  349. -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
  350. fprintf (stream, _("\
  351. -no-warn-unmatched-high do not warn about missing low relocs\n"));
  352. fprintf (stream, _("\
  353. -Wuh synonym for -warn-unmatched-high\n"));
  354. fprintf (stream, _("\
  355. -Wnuh synonym for -no-warn-unmatched-high\n"));
  356. fprintf (stream, _("\
  357. -KPIC generate PIC\n"));
  358. }
  359. /* Set by md_assemble for use by m32r_fill_insn. */
  360. static subsegT prev_subseg;
  361. static segT prev_seg;
  362. #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
  363. symbolS * GOT_symbol;
  364. static inline int
  365. m32r_PIC_related_p (symbolS *sym)
  366. {
  367. expressionS *exp;
  368. if (! sym)
  369. return 0;
  370. if (sym == GOT_symbol)
  371. return 1;
  372. exp = symbol_get_value_expression (sym);
  373. return (exp->X_op == O_PIC_reloc
  374. || exp->X_md == BFD_RELOC_M32R_26_PLTREL
  375. || m32r_PIC_related_p (exp->X_add_symbol)
  376. || m32r_PIC_related_p (exp->X_op_symbol));
  377. }
  378. static inline int
  379. m32r_check_fixup (expressionS *main_exp, bfd_reloc_code_real_type *r_type_p)
  380. {
  381. expressionS *exp = main_exp;
  382. if (exp->X_op == O_add && m32r_PIC_related_p (exp->X_op_symbol))
  383. return 1;
  384. if (exp->X_op == O_symbol && exp->X_add_symbol)
  385. {
  386. if (exp->X_add_symbol == GOT_symbol)
  387. {
  388. *r_type_p = BFD_RELOC_M32R_GOTPC24;
  389. return 0;
  390. }
  391. }
  392. else if (exp->X_op == O_add)
  393. {
  394. exp = symbol_get_value_expression (exp->X_add_symbol);
  395. if (! exp)
  396. return 0;
  397. }
  398. if (exp->X_op == O_PIC_reloc)
  399. {
  400. *r_type_p = exp->X_md;
  401. if (exp == main_exp)
  402. exp->X_op = O_symbol;
  403. else
  404. {
  405. main_exp->X_add_symbol = exp->X_add_symbol;
  406. main_exp->X_add_number += exp->X_add_number;
  407. }
  408. }
  409. else
  410. return (m32r_PIC_related_p (exp->X_add_symbol)
  411. || m32r_PIC_related_p (exp->X_op_symbol));
  412. return 0;
  413. }
  414. /* FIXME: Should be machine generated. */
  415. #define NOP_INSN 0x7000
  416. #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */
  417. /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
  418. of an rs_align_code fragment. */
  419. void
  420. m32r_handle_align (fragS *fragp)
  421. {
  422. static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
  423. static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 };
  424. int bytes, fix;
  425. char *p;
  426. if (fragp->fr_type != rs_align_code)
  427. return;
  428. bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
  429. p = fragp->fr_literal + fragp->fr_fix;
  430. fix = 0;
  431. if (bytes & 1)
  432. {
  433. fix = 1;
  434. *p++ = 0;
  435. bytes--;
  436. }
  437. if (bytes & 2)
  438. {
  439. memcpy (p, nop_pattern, 2);
  440. p += 2;
  441. bytes -= 2;
  442. fix += 2;
  443. }
  444. memcpy (p, multi_nop_pattern, 4);
  445. fragp->fr_fix += fix;
  446. fragp->fr_var = 4;
  447. }
  448. /* If the last instruction was the first of 2 16 bit insns,
  449. output a nop to move the PC to a 32 bit boundary.
  450. This is done via an alignment specification since branch relaxing
  451. may make it unnecessary.
  452. Internally, we need to output one of these each time a 32 bit insn is
  453. seen after an insn that is relaxable. */
  454. static void
  455. fill_insn (int ignore ATTRIBUTE_UNUSED)
  456. {
  457. frag_align_code (2, 0);
  458. prev_insn.insn = NULL;
  459. seen_relaxable_p = 0;
  460. }
  461. /* Record the symbol so that when we output the insn, we can create
  462. a symbol that is at the start of the instruction. This is used
  463. to emit the label for the start of a breakpoint without causing
  464. the assembler to emit a NOP if the previous instruction was a
  465. 16 bit instruction. */
  466. static void
  467. debug_sym (int ignore ATTRIBUTE_UNUSED)
  468. {
  469. char *name;
  470. char delim;
  471. symbolS *symbolP;
  472. sym_linkS *lnk;
  473. delim = get_symbol_name (&name);
  474. if ((symbolP = symbol_find (name)) == NULL
  475. && (symbolP = md_undefined_symbol (name)) == NULL)
  476. symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
  477. symbol_table_insert (symbolP);
  478. if (S_IS_DEFINED (symbolP) && (S_GET_SEGMENT (symbolP) != reg_section
  479. || S_IS_EXTERNAL (symbolP)
  480. || S_IS_WEAK (symbolP)))
  481. /* xgettext:c-format */
  482. as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
  483. else
  484. {
  485. lnk = (sym_linkS *) xmalloc (sizeof (sym_linkS));
  486. lnk->symbol = symbolP;
  487. lnk->next = debug_sym_link;
  488. debug_sym_link = lnk;
  489. symbol_get_obj (symbolP)->local = 1;
  490. }
  491. (void) restore_line_pointer (delim);
  492. demand_empty_rest_of_line ();
  493. }
  494. /* Second pass to expanding the debug symbols, go through linked
  495. list of symbols and reassign the address. */
  496. static void
  497. expand_debug_syms (sym_linkS *syms, int align)
  498. {
  499. char *save_input_line = input_line_pointer;
  500. sym_linkS *next_syms;
  501. if (!syms)
  502. return;
  503. (void) frag_align_code (align, 0);
  504. for (; syms != (sym_linkS *) 0; syms = next_syms)
  505. {
  506. symbolS *symbolP = syms->symbol;
  507. next_syms = syms->next;
  508. input_line_pointer = ".\n";
  509. pseudo_set (symbolP);
  510. free ((char *) syms);
  511. }
  512. input_line_pointer = save_input_line;
  513. }
  514. void
  515. m32r_flush_pending_output (void)
  516. {
  517. if (debug_sym_link)
  518. {
  519. expand_debug_syms (debug_sym_link, 1);
  520. debug_sym_link = (sym_linkS *) 0;
  521. }
  522. }
  523. /* Cover function to fill_insn called after a label and at end of assembly.
  524. The result is always 1: we're called in a conditional to see if the
  525. current line is a label. */
  526. int
  527. m32r_fill_insn (int done)
  528. {
  529. if (prev_seg != NULL)
  530. {
  531. segT seg = now_seg;
  532. subsegT subseg = now_subseg;
  533. subseg_set (prev_seg, prev_subseg);
  534. fill_insn (0);
  535. subseg_set (seg, subseg);
  536. }
  537. if (done && debug_sym_link)
  538. {
  539. expand_debug_syms (debug_sym_link, 1);
  540. debug_sym_link = (sym_linkS *) 0;
  541. }
  542. return 1;
  543. }
  544. /* The default target format to use. */
  545. const char *
  546. m32r_target_format (void)
  547. {
  548. #ifdef TE_LINUX
  549. if (target_big_endian)
  550. return "elf32-m32r-linux";
  551. else
  552. return "elf32-m32rle-linux";
  553. #else
  554. if (target_big_endian)
  555. return "elf32-m32r";
  556. else
  557. return "elf32-m32rle";
  558. #endif
  559. }
  560. void
  561. md_begin (void)
  562. {
  563. flagword applicable;
  564. segT seg;
  565. subsegT subseg;
  566. /* Initialize the `cgen' interface. */
  567. /* Set the machine number and endian. */
  568. gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
  569. CGEN_CPU_OPEN_ENDIAN,
  570. (target_big_endian ?
  571. CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE),
  572. CGEN_CPU_OPEN_END);
  573. m32r_cgen_init_asm (gas_cgen_cpu_desc);
  574. /* The operand instance table is used during optimization to determine
  575. which insns can be executed in parallel. It is also used to give
  576. warnings regarding operand interference in parallel insns. */
  577. m32r_cgen_init_opinst_table (gas_cgen_cpu_desc);
  578. /* This is a callback from cgen to gas to parse operands. */
  579. cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
  580. /* Save the current subseg so we can restore it [it's the default one and
  581. we don't want the initial section to be .sbss]. */
  582. seg = now_seg;
  583. subseg = now_subseg;
  584. /* The sbss section is for local .scomm symbols. */
  585. sbss_section = subseg_new (".sbss", 0);
  586. seg_info (sbss_section)->bss = 1;
  587. /* This is copied from perform_an_assembly_pass. */
  588. applicable = bfd_applicable_section_flags (stdoutput);
  589. bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
  590. subseg_set (seg, subseg);
  591. /* We must construct a fake section similar to bfd_com_section
  592. but with the name .scommon. */
  593. scom_section = *bfd_com_section_ptr;
  594. scom_section.name = ".scommon";
  595. scom_section.output_section = & scom_section;
  596. scom_section.symbol = & scom_symbol;
  597. scom_section.symbol_ptr_ptr = & scom_section.symbol;
  598. scom_symbol = * bfd_com_section_ptr->symbol;
  599. scom_symbol.name = ".scommon";
  600. scom_symbol.section = & scom_section;
  601. allow_m32rx (enable_m32rx);
  602. gas_cgen_initialize_saved_fixups_array ();
  603. }
  604. #define OPERAND_IS_COND_BIT(operand, indices, index) \
  605. ((operand)->hw_type == HW_H_COND \
  606. || ((operand)->hw_type == HW_H_PSW) \
  607. || ((operand)->hw_type == HW_H_CR \
  608. && (indices [index] == 0 || indices [index] == 1)))
  609. /* Returns true if an output of instruction 'a' is referenced by an operand
  610. of instruction 'b'. If 'check_outputs' is true then b's outputs are
  611. checked, otherwise its inputs are examined. */
  612. static int
  613. first_writes_to_seconds_operands (m32r_insn *a,
  614. m32r_insn *b,
  615. const int check_outputs)
  616. {
  617. const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn);
  618. const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn);
  619. int a_index;
  620. if (ignore_parallel_conflicts)
  621. return 0;
  622. /* If at least one of the instructions takes no operands, then there is
  623. nothing to check. There really are instructions without operands,
  624. eg 'nop'. */
  625. if (a_operands == NULL || b_ops == NULL)
  626. return 0;
  627. /* Scan the operand list of 'a' looking for an output operand. */
  628. for (a_index = 0;
  629. a_operands->type != CGEN_OPINST_END;
  630. a_index ++, a_operands ++)
  631. {
  632. if (a_operands->type == CGEN_OPINST_OUTPUT)
  633. {
  634. int b_index;
  635. const CGEN_OPINST *b_operands = b_ops;
  636. /* Special Case:
  637. The Condition bit 'C' is a shadow of the CBR register (control
  638. register 1) and also a shadow of bit 31 of the program status
  639. word (control register 0). For now this is handled here, rather
  640. than by cgen.... */
  641. if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index))
  642. {
  643. /* Scan operand list of 'b' looking for another reference to the
  644. condition bit, which goes in the right direction. */
  645. for (b_index = 0;
  646. b_operands->type != CGEN_OPINST_END;
  647. b_index++, b_operands++)
  648. {
  649. if ((b_operands->type
  650. == (check_outputs
  651. ? CGEN_OPINST_OUTPUT
  652. : CGEN_OPINST_INPUT))
  653. && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index))
  654. return 1;
  655. }
  656. }
  657. else
  658. {
  659. /* Scan operand list of 'b' looking for an operand that
  660. references the same hardware element, and which goes in the
  661. right direction. */
  662. for (b_index = 0;
  663. b_operands->type != CGEN_OPINST_END;
  664. b_index++, b_operands++)
  665. {
  666. if ((b_operands->type
  667. == (check_outputs
  668. ? CGEN_OPINST_OUTPUT
  669. : CGEN_OPINST_INPUT))
  670. && (b_operands->hw_type == a_operands->hw_type)
  671. && (a->indices[a_index] == b->indices[b_index]))
  672. return 1;
  673. }
  674. }
  675. }
  676. }
  677. return 0;
  678. }
  679. /* Returns true if the insn can (potentially) alter the program counter. */
  680. static int
  681. writes_to_pc (m32r_insn *a)
  682. {
  683. if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI)
  684. || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI))
  685. return 1;
  686. return 0;
  687. }
  688. /* Return NULL if the two 16 bit insns can be executed in parallel.
  689. Otherwise return a pointer to an error message explaining why not. */
  690. static const char *
  691. can_make_parallel (m32r_insn *a, m32r_insn *b)
  692. {
  693. PIPE_ATTR a_pipe;
  694. PIPE_ATTR b_pipe;
  695. /* Make sure the instructions are the right length. */
  696. if (CGEN_FIELDS_BITSIZE (&a->fields) != 16
  697. || CGEN_FIELDS_BITSIZE (&b->fields) != 16)
  698. abort ();
  699. if (first_writes_to_seconds_operands (a, b, TRUE))
  700. return _("instructions write to the same destination register.");
  701. a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE);
  702. b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE);
  703. /* Make sure that the instructions use the correct execution pipelines. */
  704. if (a_pipe == PIPE_NONE
  705. || b_pipe == PIPE_NONE)
  706. return _("Instructions do not use parallel execution pipelines.");
  707. /* Leave this test for last, since it is the only test that can
  708. go away if the instructions are swapped, and we want to make
  709. sure that any other errors are detected before this happens. */
  710. if (a_pipe == PIPE_S
  711. || b_pipe == PIPE_O
  712. || (b_pipe == PIPE_O_OS && (enable_m32rx != 2)))
  713. return _("Instructions share the same execution pipeline");
  714. return NULL;
  715. }
  716. /* Force the top bit of the second 16-bit insn to be set. */
  717. static void
  718. make_parallel (CGEN_INSN_BYTES_PTR buffer)
  719. {
  720. #if CGEN_INT_INSN_P
  721. *buffer |= 0x8000;
  722. #else
  723. buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
  724. |= 0x80;
  725. #endif
  726. }
  727. /* Same as make_parallel except buffer contains the bytes in target order. */
  728. static void
  729. target_make_parallel (char *buffer)
  730. {
  731. buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
  732. |= 0x80;
  733. }
  734. /* Assemble two instructions with an explicit parallel operation (||) or
  735. sequential operation (->). */
  736. static void
  737. assemble_two_insns (char *str1, char *str2, int parallel_p)
  738. {
  739. char *str3;
  740. m32r_insn first;
  741. m32r_insn second;
  742. char *errmsg;
  743. char save_str2 = *str2;
  744. /* Separate the two instructions. */
  745. *str2 = 0;
  746. /* Make sure the two insns begin on a 32 bit boundary.
  747. This is also done for the serial case (foo -> bar), relaxing doesn't
  748. affect insns written like this.
  749. Note that we must always do this as we can't assume anything about
  750. whether we're currently on a 32 bit boundary or not. Relaxing may
  751. change this. */
  752. fill_insn (0);
  753. first.debug_sym_link = debug_sym_link;
  754. debug_sym_link = (sym_linkS *) 0;
  755. /* Parse the first instruction. */
  756. if (! (first.insn = m32r_cgen_assemble_insn
  757. (gas_cgen_cpu_desc, str1, & first.fields, first.buffer, & errmsg)))
  758. {
  759. as_bad ("%s", errmsg);
  760. return;
  761. }
  762. /* Check it. */
  763. if (CGEN_FIELDS_BITSIZE (&first.fields) != 16)
  764. {
  765. /* xgettext:c-format */
  766. as_bad (_("not a 16 bit instruction '%s'"), str1);
  767. return;
  768. }
  769. #ifdef E_M32R2_ARCH
  770. else if ((enable_m32rx == 1)
  771. /* FIXME: Need standard macro to perform this test. */
  772. && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
  773. & (1 << MACH_M32R2))
  774. && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
  775. & (1 << MACH_M32RX)))))
  776. {
  777. /* xgettext:c-format */
  778. as_bad (_("instruction '%s' is for the M32R2 only"), str1);
  779. return;
  780. }
  781. else if ((! enable_special
  782. && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
  783. || (! enable_special_m32r
  784. && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)))
  785. #else
  786. else if (! enable_special
  787. && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
  788. #endif
  789. {
  790. /* xgettext:c-format */
  791. as_bad (_("unknown instruction '%s'"), str1);
  792. return;
  793. }
  794. else if (! enable_m32rx
  795. /* FIXME: Need standard macro to perform this test. */
  796. && (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
  797. == (1 << MACH_M32RX)))
  798. {
  799. /* xgettext:c-format */
  800. as_bad (_("instruction '%s' is for the M32RX only"), str1);
  801. return;
  802. }
  803. /* Check to see if this is an allowable parallel insn. */
  804. if (parallel_p
  805. && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
  806. {
  807. /* xgettext:c-format */
  808. as_bad (_("instruction '%s' cannot be executed in parallel."), str1);
  809. return;
  810. }
  811. /* Restore the original assembly text, just in case it is needed. */
  812. *str2 = save_str2;
  813. /* Save the original string pointer. */
  814. str3 = str1;
  815. /* Advanced past the parsed string. */
  816. str1 = str2 + 2;
  817. /* Remember the entire string in case it is needed for error
  818. messages. */
  819. str2 = str3;
  820. /* Convert the opcode to lower case. */
  821. {
  822. char *s2 = str1;
  823. while (ISSPACE (*s2++))
  824. continue;
  825. --s2;
  826. while (ISALNUM (*s2))
  827. {
  828. *s2 = TOLOWER (*s2);
  829. s2++;
  830. }
  831. }
  832. /* Preserve any fixups that have been generated and reset the list
  833. to empty. */
  834. gas_cgen_save_fixups (0);
  835. /* Get the indices of the operands of the instruction. */
  836. /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
  837. doesn't seem right. Perhaps allow passing fields like we do insn. */
  838. /* FIXME: ALIAS insns do not have operands, so we use this function
  839. to find the equivalent insn and overwrite the value stored in our
  840. structure. We still need the original insn, however, since this
  841. may have certain attributes that are not present in the unaliased
  842. version (eg relaxability). When aliases behave differently this
  843. may have to change. */
  844. first.orig_insn = first.insn;
  845. {
  846. CGEN_FIELDS tmp_fields;
  847. first.insn = cgen_lookup_get_insn_operands
  848. (gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16,
  849. first.indices, &tmp_fields);
  850. }
  851. if (first.insn == NULL)
  852. as_fatal (_("internal error: lookup/get operands failed"));
  853. second.debug_sym_link = NULL;
  854. /* Parse the second instruction. */
  855. if (! (second.insn = m32r_cgen_assemble_insn
  856. (gas_cgen_cpu_desc, str1, & second.fields, second.buffer, & errmsg)))
  857. {
  858. as_bad ("%s", errmsg);
  859. return;
  860. }
  861. /* Check it. */
  862. if (CGEN_FIELDS_BITSIZE (&second.fields) != 16)
  863. {
  864. /* xgettext:c-format */
  865. as_bad (_("not a 16 bit instruction '%s'"), str1);
  866. return;
  867. }
  868. #ifdef E_M32R2_ARCH
  869. else if ((enable_m32rx == 1)
  870. /* FIXME: Need standard macro to perform this test. */
  871. && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
  872. & (1 << MACH_M32R2))
  873. && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
  874. & (1 << MACH_M32RX)))))
  875. {
  876. /* xgettext:c-format */
  877. as_bad (_("instruction '%s' is for the M32R2 only"), str1);
  878. return;
  879. }
  880. else if ((! enable_special
  881. && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
  882. || (! enable_special_m32r
  883. && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R)))
  884. #else
  885. else if (! enable_special
  886. && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
  887. #endif
  888. {
  889. /* xgettext:c-format */
  890. as_bad (_("unknown instruction '%s'"), str1);
  891. return;
  892. }
  893. else if (! enable_m32rx
  894. && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
  895. {
  896. /* xgettext:c-format */
  897. as_bad (_("instruction '%s' is for the M32RX only"), str1);
  898. return;
  899. }
  900. /* Check to see if this is an allowable parallel insn. */
  901. if (parallel_p
  902. && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
  903. {
  904. /* xgettext:c-format */
  905. as_bad (_("instruction '%s' cannot be executed in parallel."), str1);
  906. return;
  907. }
  908. if (parallel_p && ! enable_m32rx)
  909. {
  910. if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP
  911. && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP)
  912. {
  913. /* xgettext:c-format */
  914. as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2);
  915. return;
  916. }
  917. }
  918. /* Get the indices of the operands of the instruction. */
  919. second.orig_insn = second.insn;
  920. {
  921. CGEN_FIELDS tmp_fields;
  922. second.insn = cgen_lookup_get_insn_operands
  923. (gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16,
  924. second.indices, &tmp_fields);
  925. }
  926. if (second.insn == NULL)
  927. as_fatal (_("internal error: lookup/get operands failed"));
  928. /* We assume that if the first instruction writes to a register that is
  929. read by the second instruction it is because the programmer intended
  930. this to happen, (after all they have explicitly requested that these
  931. two instructions be executed in parallel). Although if the global
  932. variable warn_explicit_parallel_conflicts is true then we do generate
  933. a warning message. Similarly we assume that parallel branch and jump
  934. instructions are deliberate and should not produce errors. */
  935. if (parallel_p && warn_explicit_parallel_conflicts)
  936. {
  937. if (first_writes_to_seconds_operands (&first, &second, FALSE))
  938. /* xgettext:c-format */
  939. as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2);
  940. if (first_writes_to_seconds_operands (&second, &first, FALSE))
  941. /* xgettext:c-format */
  942. as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
  943. }
  944. if (!parallel_p
  945. || (errmsg = (char *) can_make_parallel (&first, &second)) == NULL)
  946. {
  947. /* Get the fixups for the first instruction. */
  948. gas_cgen_swap_fixups (0);
  949. /* Write it out. */
  950. expand_debug_syms (first.debug_sym_link, 1);
  951. gas_cgen_finish_insn (first.orig_insn, first.buffer,
  952. CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL);
  953. /* Force the top bit of the second insn to be set. */
  954. if (parallel_p)
  955. make_parallel (second.buffer);
  956. /* Get its fixups. */
  957. gas_cgen_restore_fixups (0);
  958. /* Write it out. */
  959. expand_debug_syms (second.debug_sym_link, 1);
  960. gas_cgen_finish_insn (second.orig_insn, second.buffer,
  961. CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL);
  962. }
  963. /* Try swapping the instructions to see if they work that way. */
  964. else if (can_make_parallel (&second, &first) == NULL)
  965. {
  966. /* Write out the second instruction first. */
  967. expand_debug_syms (second.debug_sym_link, 1);
  968. gas_cgen_finish_insn (second.orig_insn, second.buffer,
  969. CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL);
  970. /* Force the top bit of the first instruction to be set. */
  971. make_parallel (first.buffer);
  972. /* Get the fixups for the first instruction. */
  973. gas_cgen_restore_fixups (0);
  974. /* Write out the first instruction. */
  975. expand_debug_syms (first.debug_sym_link, 1);
  976. gas_cgen_finish_insn (first.orig_insn, first.buffer,
  977. CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL);
  978. }
  979. else
  980. {
  981. as_bad ("'%s': %s", str2, errmsg);
  982. return;
  983. }
  984. if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)
  985. || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
  986. m32r_flags |= E_M32R_HAS_HIDDEN_INST;
  987. if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)
  988. || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R))
  989. m32r_flags |= E_M32R_HAS_BIT_INST;
  990. if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_FLOAT)
  991. || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_FLOAT))
  992. m32r_flags |= E_M32R_HAS_FLOAT_INST;
  993. /* Set these so m32r_fill_insn can use them. */
  994. prev_seg = now_seg;
  995. prev_subseg = now_subseg;
  996. }
  997. void
  998. md_assemble (char *str)
  999. {
  1000. m32r_insn insn;
  1001. char *errmsg;
  1002. char *str2 = NULL;
  1003. /* Initialize GAS's cgen interface for a new instruction. */
  1004. gas_cgen_init_parse ();
  1005. /* Look for a parallel instruction separator. */
  1006. if ((str2 = strstr (str, "||")) != NULL)
  1007. {
  1008. assemble_two_insns (str, str2, 1);
  1009. m32r_flags |= E_M32R_HAS_PARALLEL;
  1010. return;
  1011. }
  1012. /* Also look for a sequential instruction separator. */
  1013. if ((str2 = strstr (str, "->")) != NULL)
  1014. {
  1015. assemble_two_insns (str, str2, 0);
  1016. return;
  1017. }
  1018. insn.debug_sym_link = debug_sym_link;
  1019. debug_sym_link = (sym_linkS *) 0;
  1020. insn.insn = m32r_cgen_assemble_insn
  1021. (gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg);
  1022. if (!insn.insn)
  1023. {
  1024. as_bad ("%s", errmsg);
  1025. return;
  1026. }
  1027. #ifdef E_M32R2_ARCH
  1028. if ((enable_m32rx == 1)
  1029. /* FIXME: Need standard macro to perform this test. */
  1030. && ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)
  1031. & (1 << MACH_M32R2))
  1032. && !((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)
  1033. & (1 << MACH_M32RX)))))
  1034. {
  1035. /* xgettext:c-format */
  1036. as_bad (_("instruction '%s' is for the M32R2 only"), str);
  1037. return;
  1038. }
  1039. else if ((! enable_special
  1040. && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
  1041. || (! enable_special_m32r
  1042. && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R)))
  1043. #else
  1044. if (! enable_special
  1045. && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
  1046. #endif
  1047. {
  1048. /* xgettext:c-format */
  1049. as_bad (_("unknown instruction '%s'"), str);
  1050. return;
  1051. }
  1052. else if (! enable_m32rx
  1053. && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
  1054. {
  1055. /* xgettext:c-format */
  1056. as_bad (_("instruction '%s' is for the M32RX only"), str);
  1057. return;
  1058. }
  1059. if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
  1060. m32r_flags |= E_M32R_HAS_HIDDEN_INST;
  1061. if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R))
  1062. m32r_flags |= E_M32R_HAS_BIT_INST;
  1063. if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_FLOAT))
  1064. m32r_flags |= E_M32R_HAS_FLOAT_INST;
  1065. if (CGEN_INSN_BITSIZE (insn.insn) == 32)
  1066. {
  1067. /* 32 bit insns must live on 32 bit boundaries. */
  1068. if (prev_insn.insn || seen_relaxable_p)
  1069. {
  1070. /* ??? If calling fill_insn too many times turns us into a memory
  1071. pig, can we call a fn to assemble a nop instead of
  1072. !seen_relaxable_p? */
  1073. fill_insn (0);
  1074. }
  1075. expand_debug_syms (insn.debug_sym_link, 2);
  1076. /* Doesn't really matter what we pass for RELAX_P here. */
  1077. gas_cgen_finish_insn (insn.insn, insn.buffer,
  1078. CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL);
  1079. }
  1080. else
  1081. {
  1082. int on_32bit_boundary_p;
  1083. int swap = FALSE;
  1084. if (CGEN_INSN_BITSIZE (insn.insn) != 16)
  1085. abort ();
  1086. insn.orig_insn = insn.insn;
  1087. /* If the previous insn was relaxable, then it may be expanded
  1088. to fill the current 16 bit slot. Emit a NOP here to occupy
  1089. this slot, so that we can start at optimizing at a 32 bit
  1090. boundary. */
  1091. if (prev_insn.insn && seen_relaxable_p && optimize)
  1092. fill_insn (0);
  1093. if (enable_m32rx)
  1094. {
  1095. /* Get the indices of the operands of the instruction.
  1096. FIXME: See assemble_parallel for notes on orig_insn. */
  1097. {
  1098. CGEN_FIELDS tmp_fields;
  1099. insn.insn = cgen_lookup_get_insn_operands
  1100. (gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL,
  1101. 16, insn.indices, &tmp_fields);
  1102. }
  1103. if (insn.insn == NULL)
  1104. as_fatal (_("internal error: lookup/get operands failed"));
  1105. }
  1106. /* Compute whether we're on a 32 bit boundary or not.
  1107. prev_insn.insn is NULL when we're on a 32 bit boundary. */
  1108. on_32bit_boundary_p = prev_insn.insn == NULL;
  1109. /* Change a frag to, if each insn to swap is in a different frag.
  1110. It must keep only one instruction in a frag. */
  1111. if (parallel() && on_32bit_boundary_p)
  1112. {
  1113. frag_wane (frag_now);
  1114. frag_new (0);
  1115. }
  1116. /* Look to see if this instruction can be combined with the
  1117. previous instruction to make one, parallel, 32 bit instruction.
  1118. If the previous instruction (potentially) changed the flow of
  1119. program control, then it cannot be combined with the current
  1120. instruction. If the current instruction is relaxable, then it
  1121. might be replaced with a longer version, so we cannot combine it.
  1122. Also if the output of the previous instruction is used as an
  1123. input to the current instruction then it cannot be combined.
  1124. Otherwise call can_make_parallel() with both orderings of the
  1125. instructions to see if they can be combined. */
  1126. if (! on_32bit_boundary_p
  1127. && parallel ()
  1128. && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
  1129. && ! writes_to_pc (&prev_insn)
  1130. && ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE))
  1131. {
  1132. if (can_make_parallel (&prev_insn, &insn) == NULL)
  1133. make_parallel (insn.buffer);
  1134. else if (can_make_parallel (&insn, &prev_insn) == NULL)
  1135. swap = TRUE;
  1136. }
  1137. expand_debug_syms (insn.debug_sym_link, 1);
  1138. {
  1139. int i;
  1140. finished_insnS fi;
  1141. /* Ensure each pair of 16 bit insns is in the same frag. */
  1142. frag_grow (4);
  1143. gas_cgen_finish_insn (insn.orig_insn, insn.buffer,
  1144. CGEN_FIELDS_BITSIZE (&insn.fields),
  1145. 1 /* relax_p */, &fi);
  1146. insn.addr = fi.addr;
  1147. insn.frag = fi.frag;
  1148. insn.num_fixups = fi.num_fixups;
  1149. for (i = 0; i < fi.num_fixups; ++i)
  1150. insn.fixups[i] = fi.fixups[i];
  1151. }
  1152. if (swap)
  1153. {
  1154. int i, tmp;
  1155. #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
  1156. /* Swap the two insns */
  1157. SWAP_BYTES (prev_insn.addr[0], insn.addr[0]);
  1158. SWAP_BYTES (prev_insn.addr[1], insn.addr[1]);
  1159. target_make_parallel (insn.addr);
  1160. /* Swap any relaxable frags recorded for the two insns. */
  1161. /* FIXME: Clarify. relaxation precludes parallel insns */
  1162. if (prev_insn.frag->fr_opcode == prev_insn.addr)
  1163. prev_insn.frag->fr_opcode = insn.addr;
  1164. else if (insn.frag->fr_opcode == insn.addr)
  1165. insn.frag->fr_opcode = prev_insn.addr;
  1166. /* Change a frag to, if each insn is in a different frag.
  1167. It must keep only one instruction in a frag. */
  1168. if (prev_insn.frag != insn.frag)
  1169. {
  1170. for (i = 0; i < prev_insn.num_fixups; ++i)
  1171. prev_insn.fixups[i]->fx_frag = insn.frag;
  1172. for (i = 0; i < insn.num_fixups; ++i)
  1173. insn.fixups[i]->fx_frag = prev_insn.frag;
  1174. }
  1175. else
  1176. {
  1177. /* Update the addresses in any fixups.
  1178. Note that we don't have to handle the case where each insn is in
  1179. a different frag as we ensure they're in the same frag above. */
  1180. for (i = 0; i < prev_insn.num_fixups; ++i)
  1181. prev_insn.fixups[i]->fx_where += 2;
  1182. for (i = 0; i < insn.num_fixups; ++i)
  1183. insn.fixups[i]->fx_where -= 2;
  1184. }
  1185. }
  1186. /* Keep track of whether we've seen a pair of 16 bit insns.
  1187. prev_insn.insn is NULL when we're on a 32 bit boundary. */
  1188. if (on_32bit_boundary_p)
  1189. prev_insn = insn;
  1190. else
  1191. prev_insn.insn = NULL;
  1192. /* If the insn needs the following one to be on a 32 bit boundary
  1193. (e.g. subroutine calls), fill this insn's slot. */
  1194. if (on_32bit_boundary_p
  1195. && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0)
  1196. fill_insn (0);
  1197. /* If this is a relaxable insn (can be replaced with a larger version)
  1198. mark the fact so that we can emit an alignment directive for a
  1199. following 32 bit insn if we see one. */
  1200. if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0)
  1201. seen_relaxable_p = 1;
  1202. }
  1203. /* Set these so m32r_fill_insn can use them. */
  1204. prev_seg = now_seg;
  1205. prev_subseg = now_subseg;
  1206. }
  1207. /* The syntax in the manual says constants begin with '#'.
  1208. We just ignore it. */
  1209. void
  1210. md_operand (expressionS *expressionP)
  1211. {
  1212. if (*input_line_pointer == '#')
  1213. {
  1214. input_line_pointer++;
  1215. expression (expressionP);
  1216. }
  1217. }
  1218. valueT
  1219. md_section_align (segT segment, valueT size)
  1220. {
  1221. int align = bfd_get_section_alignment (stdoutput, segment);
  1222. return ((size + (1 << align) - 1) & (-1 << align));
  1223. }
  1224. symbolS *
  1225. md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
  1226. {
  1227. return 0;
  1228. }
  1229. /* .scomm pseudo-op handler.
  1230. This is a new pseudo-op to handle putting objects in .scommon.
  1231. By doing this the linker won't need to do any work,
  1232. and more importantly it removes the implicit -G arg necessary to
  1233. correctly link the object file. */
  1234. static void
  1235. m32r_scomm (int ignore ATTRIBUTE_UNUSED)
  1236. {
  1237. char *name;
  1238. char c;
  1239. char *p;
  1240. offsetT size;
  1241. symbolS *symbolP;
  1242. offsetT align;
  1243. int align2;
  1244. c = get_symbol_name (&name);
  1245. /* Just after name is now '\0'. */
  1246. p = input_line_pointer;
  1247. *p = c;
  1248. SKIP_WHITESPACE_AFTER_NAME ();
  1249. if (*input_line_pointer != ',')
  1250. {
  1251. as_bad (_("Expected comma after symbol-name: rest of line ignored."));
  1252. ignore_rest_of_line ();
  1253. return;
  1254. }
  1255. /* Skip ','. */
  1256. input_line_pointer++;
  1257. if ((size = get_absolute_expression ()) < 0)
  1258. {
  1259. /* xgettext:c-format */
  1260. as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size);
  1261. ignore_rest_of_line ();
  1262. return;
  1263. }
  1264. /* The third argument to .scomm is the alignment. */
  1265. if (*input_line_pointer != ',')
  1266. align = 8;
  1267. else
  1268. {
  1269. ++input_line_pointer;
  1270. align = get_absolute_expression ();
  1271. if (align <= 0)
  1272. {
  1273. as_warn (_("ignoring bad alignment"));
  1274. align = 8;
  1275. }
  1276. }
  1277. /* Convert to a power of 2 alignment. */
  1278. if (align)
  1279. {
  1280. for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2)
  1281. continue;
  1282. if (align != 1)
  1283. {
  1284. as_bad (_("Common alignment not a power of 2"));
  1285. ignore_rest_of_line ();
  1286. return;
  1287. }
  1288. }
  1289. else
  1290. align2 = 0;
  1291. *p = 0;
  1292. symbolP = symbol_find_or_make (name);
  1293. *p = c;
  1294. if (S_IS_DEFINED (symbolP))
  1295. {
  1296. /* xgettext:c-format */
  1297. as_bad (_("Ignoring attempt to re-define symbol `%s'."),
  1298. S_GET_NAME (symbolP));
  1299. ignore_rest_of_line ();
  1300. return;
  1301. }
  1302. if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
  1303. {
  1304. /* xgettext:c-format */
  1305. as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
  1306. S_GET_NAME (symbolP),
  1307. (long) S_GET_VALUE (symbolP),
  1308. (long) size);
  1309. ignore_rest_of_line ();
  1310. return;
  1311. }
  1312. if (symbol_get_obj (symbolP)->local)
  1313. {
  1314. segT old_sec = now_seg;
  1315. int old_subsec = now_subseg;
  1316. char *pfrag;
  1317. record_alignment (sbss_section, align2);
  1318. subseg_set (sbss_section, 0);
  1319. if (align2)
  1320. frag_align (align2, 0, 0);
  1321. if (S_GET_SEGMENT (symbolP) == sbss_section)
  1322. symbol_get_frag (symbolP)->fr_symbol = 0;
  1323. symbol_set_frag (symbolP, frag_now);
  1324. pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
  1325. (char *) 0);
  1326. *pfrag = 0;
  1327. S_SET_SIZE (symbolP, size);
  1328. S_SET_SEGMENT (symbolP, sbss_section);
  1329. S_CLEAR_EXTERNAL (symbolP);
  1330. subseg_set (old_sec, old_subsec);
  1331. }
  1332. else
  1333. {
  1334. S_SET_VALUE (symbolP, (valueT) size);
  1335. S_SET_ALIGN (symbolP, align2);
  1336. S_SET_EXTERNAL (symbolP);
  1337. S_SET_SEGMENT (symbolP, &scom_section);
  1338. }
  1339. demand_empty_rest_of_line ();
  1340. }
  1341. /* The target specific pseudo-ops which we support. */
  1342. const pseudo_typeS md_pseudo_table[] =
  1343. {
  1344. { "word", cons, 4 },
  1345. { "fillinsn", fill_insn, 0 },
  1346. { "scomm", m32r_scomm, 0 },
  1347. { "debugsym", debug_sym, 0 },
  1348. { "m32r", allow_m32rx, 0 },
  1349. { "m32rx", allow_m32rx, 1 },
  1350. { "m32r2", allow_m32rx, 2 },
  1351. { "little", little, 1 },
  1352. { "big", little, 0 },
  1353. { NULL, NULL, 0 }
  1354. };
  1355. /* Interface to relax_segment. */
  1356. /* FIXME: Build table by hand, get it working, then machine generate. */
  1357. const relax_typeS md_relax_table[] =
  1358. {
  1359. /* The fields are:
  1360. 1) most positive reach of this state,
  1361. 2) most negative reach of this state,
  1362. 3) how many bytes this mode will add to the size of the current frag
  1363. 4) which index into the table to try if we can't fit into this one. */
  1364. /* The first entry must be unused because an `rlx_more' value of zero ends
  1365. each list. */
  1366. {1, 1, 0, 0},
  1367. /* The displacement used by GAS is from the end of the 2 byte insn,
  1368. so we subtract 2 from the following. */
  1369. /* 16 bit insn, 8 bit disp -> 10 bit range.
  1370. This doesn't handle a branch in the right slot at the border:
  1371. the "& -4" isn't taken into account. It's not important enough to
  1372. complicate things over it, so we subtract an extra 2 (or + 2 in -ve
  1373. case). */
  1374. {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
  1375. /* 32 bit insn, 24 bit disp -> 26 bit range. */
  1376. {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
  1377. /* Same thing, but with leading nop for alignment. */
  1378. {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
  1379. };
  1380. long
  1381. m32r_relax_frag (segT segment, fragS *fragP, long stretch)
  1382. {
  1383. /* Address of branch insn. */
  1384. long address = fragP->fr_address + fragP->fr_fix - 2;
  1385. long growth = 0;
  1386. /* Keep 32 bit insns aligned on 32 bit boundaries. */
  1387. if (fragP->fr_subtype == 2)
  1388. {
  1389. if ((address & 3) != 0)
  1390. {
  1391. fragP->fr_subtype = 3;
  1392. growth = 2;
  1393. }
  1394. }
  1395. else if (fragP->fr_subtype == 3)
  1396. {
  1397. if ((address & 3) == 0)
  1398. {
  1399. fragP->fr_subtype = 2;
  1400. growth = -2;
  1401. }
  1402. }
  1403. else
  1404. {
  1405. growth = relax_frag (segment, fragP, stretch);
  1406. /* Long jump on odd halfword boundary? */
  1407. if (fragP->fr_subtype == 2 && (address & 3) != 0)
  1408. {
  1409. fragP->fr_subtype = 3;
  1410. growth += 2;
  1411. }
  1412. }
  1413. return growth;
  1414. }
  1415. /* Return an initial guess of the length by which a fragment must grow to
  1416. hold a branch to reach its destination.
  1417. Also updates fr_type/fr_subtype as necessary.
  1418. Called just before doing relaxation.
  1419. Any symbol that is now undefined will not become defined.
  1420. The guess for fr_var is ACTUALLY the growth beyond fr_fix.
  1421. Whatever we do to grow fr_fix or fr_var contributes to our returned value.
  1422. Although it may not be explicit in the frag, pretend fr_var starts
  1423. with a 0 value. */
  1424. int
  1425. md_estimate_size_before_relax (fragS *fragP, segT segment)
  1426. {
  1427. /* The only thing we have to handle here are symbols outside of the
  1428. current segment. They may be undefined or in a different segment in
  1429. which case linker scripts may place them anywhere.
  1430. However, we can't finish the fragment here and emit the reloc as insn
  1431. alignment requirements may move the insn about. */
  1432. if (S_GET_SEGMENT (fragP->fr_symbol) != segment
  1433. || S_IS_EXTERNAL (fragP->fr_symbol)
  1434. || S_IS_WEAK (fragP->fr_symbol))
  1435. {
  1436. /* The symbol is undefined in this segment.
  1437. Change the relaxation subtype to the max allowable and leave
  1438. all further handling to md_convert_frag. */
  1439. fragP->fr_subtype = 2;
  1440. {
  1441. const CGEN_INSN *insn;
  1442. int i;
  1443. /* Update the recorded insn.
  1444. Fortunately we don't have to look very far.
  1445. FIXME: Change this to record in the instruction the next higher
  1446. relaxable insn to use. */
  1447. for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
  1448. {
  1449. if ((strcmp (CGEN_INSN_MNEMONIC (insn),
  1450. CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
  1451. == 0)
  1452. && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED))
  1453. break;
  1454. }
  1455. if (i == 4)
  1456. abort ();
  1457. fragP->fr_cgen.insn = insn;
  1458. return 2;
  1459. }
  1460. }
  1461. return md_relax_table[fragP->fr_subtype].rlx_length;
  1462. }
  1463. /* *FRAGP has been relaxed to its final size, and now needs to have
  1464. the bytes inside it modified to conform to the new size.
  1465. Called after relaxation is finished.
  1466. fragP->fr_type == rs_machine_dependent.
  1467. fragP->fr_subtype is the subtype of what the address relaxed to. */
  1468. void
  1469. md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
  1470. segT sec,
  1471. fragS *fragP)
  1472. {
  1473. char *opcode;
  1474. char *displacement;
  1475. int target_address;
  1476. int opcode_address;
  1477. int extension;
  1478. int addend;
  1479. opcode = fragP->fr_opcode;
  1480. /* Address opcode resides at in file space. */
  1481. opcode_address = fragP->fr_address + fragP->fr_fix - 2;
  1482. switch (fragP->fr_subtype)
  1483. {
  1484. case 1:
  1485. extension = 0;
  1486. displacement = &opcode[1];
  1487. break;
  1488. case 2:
  1489. opcode[0] |= 0x80;
  1490. extension = 2;
  1491. displacement = &opcode[1];
  1492. break;
  1493. case 3:
  1494. opcode[2] = opcode[0] | 0x80;
  1495. md_number_to_chars (opcode, PAR_NOP_INSN, 2);
  1496. opcode_address += 2;
  1497. extension = 4;
  1498. displacement = &opcode[3];
  1499. break;
  1500. default:
  1501. abort ();
  1502. }
  1503. if (S_GET_SEGMENT (fragP->fr_symbol) != sec
  1504. || S_IS_EXTERNAL (fragP->fr_symbol)
  1505. || S_IS_WEAK (fragP->fr_symbol))
  1506. {
  1507. /* Symbol must be resolved by linker. */
  1508. if (fragP->fr_offset & 3)
  1509. as_warn (_("Addend to unresolved symbol not on word boundary."));
  1510. #ifdef USE_M32R_OLD_RELOC
  1511. addend = fragP->fr_offset >> 2; /* Old M32R used USE_REL. */
  1512. #else
  1513. addend = 0;
  1514. #endif
  1515. }
  1516. else
  1517. {
  1518. /* Address we want to reach in file space. */
  1519. target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
  1520. addend = (target_address - (opcode_address & -4)) >> 2;
  1521. }
  1522. /* Create a relocation for symbols that must be resolved by the linker.
  1523. Otherwise output the completed insn. */
  1524. if (S_GET_SEGMENT (fragP->fr_symbol) != sec
  1525. || S_IS_EXTERNAL (fragP->fr_symbol)
  1526. || S_IS_WEAK (fragP->fr_symbol))
  1527. {
  1528. fixS *fixP;
  1529. gas_assert (fragP->fr_subtype != 1);
  1530. gas_assert (fragP->fr_cgen.insn != 0);
  1531. fixP = gas_cgen_record_fixup (fragP,
  1532. /* Offset of branch insn in frag. */
  1533. fragP->fr_fix + extension - 4,
  1534. fragP->fr_cgen.insn,
  1535. 4 /* Length. */,
  1536. /* FIXME: quick hack. */
  1537. cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
  1538. M32R_OPERAND_DISP24),
  1539. fragP->fr_cgen.opinfo,
  1540. fragP->fr_symbol, fragP->fr_offset);
  1541. if (fragP->fr_cgen.opinfo)
  1542. fixP->fx_r_type = fragP->fr_cgen.opinfo;
  1543. }
  1544. #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
  1545. md_number_to_chars (displacement, (valueT) addend,
  1546. SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
  1547. fragP->fr_fix += extension;
  1548. }
  1549. /* Functions concerning relocs. */
  1550. /* The location from which a PC relative jump should be calculated,
  1551. given a PC relative reloc. */
  1552. long
  1553. md_pcrel_from_section (fixS *fixP, segT sec)
  1554. {
  1555. if (fixP->fx_addsy != (symbolS *) NULL
  1556. && (! S_IS_DEFINED (fixP->fx_addsy)
  1557. || S_GET_SEGMENT (fixP->fx_addsy) != sec
  1558. || S_IS_EXTERNAL (fixP->fx_addsy)
  1559. || S_IS_WEAK (fixP->fx_addsy)))
  1560. {
  1561. if (S_GET_SEGMENT (fixP->fx_addsy) != sec
  1562. && S_IS_DEFINED (fixP->fx_addsy)
  1563. && ! S_IS_EXTERNAL (fixP->fx_addsy)
  1564. && ! S_IS_WEAK (fixP->fx_addsy))
  1565. return fixP->fx_offset;
  1566. /* The symbol is undefined (or is defined but not in this section).
  1567. Let the linker figure it out. */
  1568. return 0;
  1569. }
  1570. return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
  1571. }
  1572. /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
  1573. Returns BFD_RELOC_NONE if no reloc type can be found.
  1574. *FIXP may be modified if desired. */
  1575. bfd_reloc_code_real_type
  1576. md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
  1577. const CGEN_OPERAND *operand,
  1578. fixS *fixP)
  1579. {
  1580. switch (operand->type)
  1581. {
  1582. case M32R_OPERAND_DISP8: return BFD_RELOC_M32R_10_PCREL;
  1583. case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL;
  1584. case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL;
  1585. case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24;
  1586. case M32R_OPERAND_HI16:
  1587. case M32R_OPERAND_SLO16:
  1588. case M32R_OPERAND_ULO16:
  1589. /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
  1590. if (fixP->fx_cgen.opinfo != 0)
  1591. return fixP->fx_cgen.opinfo;
  1592. break;
  1593. default:
  1594. /* Avoid -Wall warning. */
  1595. break;
  1596. }
  1597. return BFD_RELOC_NONE;
  1598. }
  1599. /* Record a HI16 reloc for later matching with its LO16 cousin. */
  1600. static void
  1601. m32r_record_hi16 (int reloc_type,
  1602. fixS *fixP,
  1603. segT seg ATTRIBUTE_UNUSED)
  1604. {
  1605. struct m32r_hi_fixup *hi_fixup;
  1606. gas_assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
  1607. || reloc_type == BFD_RELOC_M32R_HI16_ULO);
  1608. hi_fixup = xmalloc (sizeof (* hi_fixup));
  1609. hi_fixup->fixp = fixP;
  1610. hi_fixup->seg = now_seg;
  1611. hi_fixup->next = m32r_hi_fixup_list;
  1612. m32r_hi_fixup_list = hi_fixup;
  1613. }
  1614. /* Called while parsing an instruction to create a fixup.
  1615. We need to check for HI16 relocs and queue them up for later sorting. */
  1616. fixS *
  1617. m32r_cgen_record_fixup_exp (fragS *frag,
  1618. int where,
  1619. const CGEN_INSN *insn,
  1620. int length,
  1621. const CGEN_OPERAND *operand,
  1622. int opinfo,
  1623. expressionS *exp)
  1624. {
  1625. fixS *fixP;
  1626. bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED;
  1627. if (m32r_check_fixup (exp, &r_type))
  1628. as_bad (_("Invalid PIC expression."));
  1629. fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
  1630. operand, opinfo, exp);
  1631. switch (operand->type)
  1632. {
  1633. case M32R_OPERAND_HI16:
  1634. /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
  1635. if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO
  1636. || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
  1637. m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg);
  1638. break;
  1639. default:
  1640. /* Avoid -Wall warning. */
  1641. break;
  1642. }
  1643. switch (r_type)
  1644. {
  1645. case BFD_RELOC_UNUSED:
  1646. default:
  1647. return fixP;
  1648. case BFD_RELOC_M32R_GOTPC24:
  1649. if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
  1650. r_type = BFD_RELOC_M32R_GOTPC_HI_SLO;
  1651. else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
  1652. r_type = BFD_RELOC_M32R_GOTPC_HI_ULO;
  1653. else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
  1654. r_type = BFD_RELOC_M32R_GOTPC_LO;
  1655. break;
  1656. case BFD_RELOC_M32R_GOT24:
  1657. if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
  1658. r_type = BFD_RELOC_M32R_GOT16_HI_SLO;
  1659. else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
  1660. r_type = BFD_RELOC_M32R_GOT16_HI_ULO;
  1661. else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
  1662. r_type = BFD_RELOC_M32R_GOT16_LO;
  1663. break;
  1664. case BFD_RELOC_M32R_GOTOFF:
  1665. if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
  1666. r_type = BFD_RELOC_M32R_GOTOFF_HI_SLO;
  1667. else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
  1668. r_type = BFD_RELOC_M32R_GOTOFF_HI_ULO;
  1669. else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
  1670. r_type = BFD_RELOC_M32R_GOTOFF_LO;
  1671. break;
  1672. case BFD_RELOC_M32R_26_PLTREL:
  1673. as_bad (_("Invalid PIC expression."));
  1674. break;
  1675. }
  1676. fixP->fx_r_type = r_type;
  1677. return fixP;
  1678. }
  1679. /* Return BFD reloc type from opinfo field in a fixS.
  1680. It's tricky using fx_r_type in m32r_frob_file because the values
  1681. are BFD_RELOC_UNUSED + operand number. */
  1682. #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
  1683. /* Sort any unmatched HI16 relocs so that they immediately precede
  1684. the corresponding LO16 reloc. This is called before md_apply_fix and
  1685. tc_gen_reloc. */
  1686. void
  1687. m32r_frob_file (void)
  1688. {
  1689. struct m32r_hi_fixup *l;
  1690. for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
  1691. {
  1692. segment_info_type *seginfo;
  1693. int pass;
  1694. gas_assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
  1695. || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
  1696. /* Check quickly whether the next fixup happens to be a matching low. */
  1697. if (l->fixp->fx_next != NULL
  1698. && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
  1699. && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
  1700. && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
  1701. continue;
  1702. /* Look through the fixups for this segment for a matching `low'.
  1703. When we find one, move the high/shigh just in front of it. We do
  1704. this in two passes. In the first pass, we try to find a
  1705. unique `low'. In the second pass, we permit multiple high's
  1706. relocs for a single `low'. */
  1707. seginfo = seg_info (l->seg);
  1708. for (pass = 0; pass < 2; pass++)
  1709. {
  1710. fixS *f;
  1711. fixS *prev;
  1712. prev = NULL;
  1713. for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
  1714. {
  1715. /* Check whether this is a `low' fixup which matches l->fixp. */
  1716. if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
  1717. && f->fx_addsy == l->fixp->fx_addsy
  1718. && f->fx_offset == l->fixp->fx_offset
  1719. && (pass == 1
  1720. || prev == NULL
  1721. || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
  1722. && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
  1723. || prev->fx_addsy != f->fx_addsy
  1724. || prev->fx_offset != f->fx_offset))
  1725. {
  1726. fixS **pf;
  1727. /* Move l->fixp before f. */
  1728. for (pf = &seginfo->fix_root;
  1729. *pf != l->fixp;
  1730. pf = & (*pf)->fx_next)
  1731. gas_assert (*pf != NULL);
  1732. *pf = l->fixp->fx_next;
  1733. l->fixp->fx_next = f;
  1734. if (prev == NULL)
  1735. seginfo->fix_root = l->fixp;
  1736. else
  1737. prev->fx_next = l->fixp;
  1738. break;
  1739. }
  1740. prev = f;
  1741. }
  1742. if (f != NULL)
  1743. break;
  1744. if (pass == 1
  1745. && warn_unmatched_high)
  1746. as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
  1747. _("Unmatched high/shigh reloc"));
  1748. }
  1749. }
  1750. }
  1751. /* See whether we need to force a relocation into the output file.
  1752. This is used to force out switch and PC relative relocations when
  1753. relaxing. */
  1754. int
  1755. m32r_force_relocation (fixS *fix)
  1756. {
  1757. if (generic_force_reloc (fix))
  1758. return 1;
  1759. if (! m32r_relax)
  1760. return 0;
  1761. return fix->fx_pcrel;
  1762. }
  1763. /* Write a value out to the object file, using the appropriate endianness. */
  1764. void
  1765. md_number_to_chars (char *buf, valueT val, int n)
  1766. {
  1767. if (target_big_endian)
  1768. number_to_chars_bigendian (buf, val, n);
  1769. else
  1770. number_to_chars_littleendian (buf, val, n);
  1771. }
  1772. /* Turn a string in input_line_pointer into a floating point constant
  1773. of type TYPE, and store the appropriate bytes in *LITP. The number
  1774. of LITTLENUMS emitted is stored in *SIZEP. An error message is
  1775. returned, or NULL on OK. */
  1776. /* Equal to MAX_PRECISION in atof-ieee.c. */
  1777. #define MAX_LITTLENUMS 6
  1778. char *
  1779. md_atof (int type, char *litP, int *sizeP)
  1780. {
  1781. return ieee_md_atof (type, litP, sizeP, target_big_endian);
  1782. }
  1783. void
  1784. m32r_elf_section_change_hook (void)
  1785. {
  1786. /* If we have reached the end of a section and we have just emitted a
  1787. 16 bit insn, then emit a nop to make sure that the section ends on
  1788. a 32 bit boundary. */
  1789. if (prev_insn.insn || seen_relaxable_p)
  1790. (void) m32r_fill_insn (0);
  1791. }
  1792. /* Return true if can adjust the reloc to be relative to its section
  1793. (such as .data) instead of relative to some symbol. */
  1794. bfd_boolean
  1795. m32r_fix_adjustable (fixS *fixP)
  1796. {
  1797. bfd_reloc_code_real_type reloc_type;
  1798. if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
  1799. {
  1800. const CGEN_INSN *insn = NULL;
  1801. int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
  1802. const CGEN_OPERAND *operand =
  1803. cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
  1804. reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
  1805. }
  1806. else
  1807. reloc_type = fixP->fx_r_type;
  1808. if (fixP->fx_addsy == NULL)
  1809. return 1;
  1810. /* Prevent all adjustments to global symbols. */
  1811. if (S_IS_EXTERNAL (fixP->fx_addsy))
  1812. return 0;
  1813. if (S_IS_WEAK (fixP->fx_addsy))
  1814. return 0;
  1815. if (pic_code
  1816. && (reloc_type == BFD_RELOC_M32R_24
  1817. || reloc_type == BFD_RELOC_M32R_26_PCREL
  1818. || reloc_type == BFD_RELOC_M32R_HI16_SLO
  1819. || reloc_type == BFD_RELOC_M32R_HI16_ULO
  1820. || reloc_type == BFD_RELOC_M32R_LO16))
  1821. return 0;
  1822. if (reloc_type == BFD_RELOC_M32R_GOT24
  1823. || reloc_type == BFD_RELOC_M32R_26_PLTREL
  1824. || reloc_type == BFD_RELOC_M32R_GOTPC_HI_SLO
  1825. || reloc_type == BFD_RELOC_M32R_GOTPC_HI_ULO
  1826. || reloc_type == BFD_RELOC_M32R_GOTPC_LO
  1827. || reloc_type == BFD_RELOC_M32R_GOT16_HI_SLO
  1828. || reloc_type == BFD_RELOC_M32R_GOT16_HI_ULO
  1829. || reloc_type == BFD_RELOC_M32R_GOT16_LO)
  1830. return 0;
  1831. /* We need the symbol name for the VTABLE entries. */
  1832. if (reloc_type == BFD_RELOC_VTABLE_INHERIT
  1833. || reloc_type == BFD_RELOC_VTABLE_ENTRY)
  1834. return 0;
  1835. return 1;
  1836. }
  1837. void
  1838. m32r_elf_final_processing (void)
  1839. {
  1840. if (use_parallel)
  1841. m32r_flags |= E_M32R_HAS_PARALLEL;
  1842. elf_elfheader (stdoutput)->e_flags |= m32r_flags;
  1843. }
  1844. /* Translate internal representation of relocation info to BFD target
  1845. format. */
  1846. arelent *
  1847. tc_gen_reloc (asection * section, fixS * fixP)
  1848. {
  1849. arelent * reloc;
  1850. bfd_reloc_code_real_type code;
  1851. reloc = xmalloc (sizeof (* reloc));
  1852. reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
  1853. *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
  1854. reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
  1855. if (fixP->fx_pcrel)
  1856. {
  1857. if (fixP->fx_r_type == BFD_RELOC_32)
  1858. fixP->fx_r_type = BFD_RELOC_32_PCREL;
  1859. else if (fixP->fx_r_type == BFD_RELOC_16)
  1860. {
  1861. fixP->fx_r_type = BFD_RELOC_16_PCREL;
  1862. bfd_set_error (bfd_error_bad_value);
  1863. }
  1864. }
  1865. code = fixP->fx_r_type;
  1866. if (pic_code)
  1867. {
  1868. #ifdef DEBUG_PIC
  1869. printf("%s",bfd_get_reloc_code_name(code));
  1870. #endif
  1871. switch (code)
  1872. {
  1873. case BFD_RELOC_M32R_26_PCREL:
  1874. code = BFD_RELOC_M32R_26_PLTREL;
  1875. break;
  1876. case BFD_RELOC_M32R_24:
  1877. if (fixP->fx_addsy != NULL
  1878. && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
  1879. code = BFD_RELOC_M32R_GOTPC24;
  1880. else
  1881. code = BFD_RELOC_M32R_GOT24;
  1882. break;
  1883. case BFD_RELOC_M32R_HI16_ULO:
  1884. if (fixP->fx_addsy != NULL
  1885. && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
  1886. code = BFD_RELOC_M32R_GOTPC_HI_ULO;
  1887. else
  1888. code = BFD_RELOC_M32R_GOT16_HI_ULO;
  1889. break;
  1890. case BFD_RELOC_M32R_HI16_SLO:
  1891. if (fixP->fx_addsy != NULL
  1892. && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
  1893. code = BFD_RELOC_M32R_GOTPC_HI_SLO;
  1894. else
  1895. code = BFD_RELOC_M32R_GOT16_HI_SLO;
  1896. break;
  1897. case BFD_RELOC_M32R_LO16:
  1898. if (fixP->fx_addsy != NULL
  1899. && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
  1900. code = BFD_RELOC_M32R_GOTPC_LO;
  1901. else
  1902. code = BFD_RELOC_M32R_GOT16_LO;
  1903. break;
  1904. default:
  1905. break;
  1906. }
  1907. #ifdef DEBUG_PIC
  1908. printf(" => %s",bfd_get_reloc_code_name(code));
  1909. #endif
  1910. }
  1911. reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
  1912. #ifdef DEBUG_PIC
  1913. printf(" => %s\n",reloc->howto->name);
  1914. #endif
  1915. if (reloc->howto == (reloc_howto_type *) NULL)
  1916. {
  1917. as_bad_where (fixP->fx_file, fixP->fx_line,
  1918. _("internal error: can't export reloc type %d (`%s')"),
  1919. fixP->fx_r_type, bfd_get_reloc_code_name (code));
  1920. return NULL;
  1921. }
  1922. /* Use fx_offset for these cases. */
  1923. if ( fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
  1924. || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
  1925. || fixP->fx_r_type == BFD_RELOC_32_PCREL)
  1926. reloc->addend = fixP->fx_offset;
  1927. else if ((!pic_code
  1928. && code != BFD_RELOC_M32R_26_PLTREL)
  1929. && fixP->fx_pcrel
  1930. && fixP->fx_addsy != NULL
  1931. && (S_GET_SEGMENT(fixP->fx_addsy) != section)
  1932. && S_IS_DEFINED (fixP->fx_addsy)
  1933. && ! S_IS_EXTERNAL(fixP->fx_addsy)
  1934. && ! S_IS_WEAK(fixP->fx_addsy))
  1935. /* Already used fx_offset in the opcode field itseld. */
  1936. reloc->addend = fixP->fx_offset;
  1937. else
  1938. reloc->addend = fixP->fx_addnumber;
  1939. return reloc;
  1940. }
  1941. inline static char *
  1942. m32r_end_of_match (char *cont, char *what)
  1943. {
  1944. int len = strlen (what);
  1945. if (strncasecmp (cont, what, strlen (what)) == 0
  1946. && ! is_part_of_name (cont[len]))
  1947. return cont + len;
  1948. return NULL;
  1949. }
  1950. int
  1951. m32r_parse_name (char const *name,
  1952. expressionS *exprP,
  1953. enum expr_mode mode,
  1954. char *nextcharP)
  1955. {
  1956. char *next = input_line_pointer;
  1957. char *next_end;
  1958. int reloc_type;
  1959. operatorT op_type;
  1960. segT segment;
  1961. exprP->X_op_symbol = NULL;
  1962. exprP->X_md = BFD_RELOC_UNUSED;
  1963. if (strcmp (name, GOT_NAME) == 0)
  1964. {
  1965. if (! GOT_symbol)
  1966. GOT_symbol = symbol_find_or_make (name);
  1967. exprP->X_add_symbol = GOT_symbol;
  1968. no_suffix:
  1969. /* If we have an absolute symbol or a
  1970. reg, then we know its value now. */
  1971. segment = S_GET_SEGMENT (exprP->X_add_symbol);
  1972. if (mode != expr_defer && segment == absolute_section)
  1973. {
  1974. exprP->X_op = O_constant;
  1975. exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
  1976. exprP->X_add_symbol = NULL;
  1977. }
  1978. else if (mode != expr_defer && segment == reg_section)
  1979. {
  1980. exprP->X_op = O_register;
  1981. exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
  1982. exprP->X_add_symbol = NULL;
  1983. }
  1984. else
  1985. {
  1986. exprP->X_op = O_symbol;
  1987. exprP->X_add_number = 0;
  1988. }
  1989. return 1;
  1990. }
  1991. exprP->X_add_symbol = symbol_find_or_make (name);
  1992. if (*nextcharP != '@')
  1993. goto no_suffix;
  1994. else if ((next_end = m32r_end_of_match (next + 1, "GOTOFF")))
  1995. {
  1996. reloc_type = BFD_RELOC_M32R_GOTOFF;
  1997. op_type = O_PIC_reloc;
  1998. }
  1999. else if ((next_end = m32r_end_of_match (next + 1, "GOT")))
  2000. {
  2001. reloc_type = BFD_RELOC_M32R_GOT24;
  2002. op_type = O_PIC_reloc;
  2003. }
  2004. else if ((next_end = m32r_end_of_match (next + 1, "PLT")))
  2005. {
  2006. reloc_type = BFD_RELOC_M32R_26_PLTREL;
  2007. op_type = O_PIC_reloc;
  2008. }
  2009. else
  2010. goto no_suffix;
  2011. *input_line_pointer = *nextcharP;
  2012. input_line_pointer = next_end;
  2013. *nextcharP = *input_line_pointer;
  2014. *input_line_pointer = '\0';
  2015. exprP->X_op = op_type;
  2016. exprP->X_add_number = 0;
  2017. exprP->X_md = reloc_type;
  2018. return 1;
  2019. }
  2020. int
  2021. m32r_cgen_parse_fix_exp(int opinfo, expressionS *exp)
  2022. {
  2023. if (exp->X_op == O_PIC_reloc
  2024. && exp->X_md == BFD_RELOC_M32R_26_PLTREL)
  2025. {
  2026. exp->X_op = O_symbol;
  2027. opinfo = exp->X_md;
  2028. }
  2029. return opinfo;
  2030. }