hisolator.pro 4.0 KB

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  1. update=Sat 30 May 2020 03:47:10 PM CST
  2. version=1
  3. last_client=kicad
  4. [general]
  5. version=1
  6. RootSch=
  7. BoardNm=
  8. [cvpcb]
  9. version=1
  10. NetIExt=net
  11. [eeschema]
  12. version=1
  13. LibDir=
  14. [eeschema/libraries]
  15. [pcbnew]
  16. version=1
  17. PageLayoutDescrFile=
  18. LastNetListRead=hisolator.net
  19. CopperLayerCount=4
  20. BoardThickness=1.6
  21. AllowMicroVias=0
  22. AllowBlindVias=0
  23. RequireCourtyardDefinitions=0
  24. ProhibitOverlappingCourtyards=1
  25. MinTrackWidth=0.127
  26. MinViaDiameter=0.5
  27. MinViaDrill=0.3
  28. MinMicroViaDiameter=0.2
  29. MinMicroViaDrill=0.09999999999999999
  30. MinHoleToHole=0.25
  31. TrackWidth1=0.2032
  32. TrackWidth2=0.146812
  33. TrackWidth3=0.508
  34. ViaDiameter1=0.5
  35. ViaDrill1=0.3
  36. dPairWidth1=0.14732
  37. dPairGap1=0.1778
  38. dPairViaGap1=0.25
  39. SilkLineWidth=0.15
  40. SilkTextSizeV=1
  41. SilkTextSizeH=1
  42. SilkTextSizeThickness=0.15
  43. SilkTextItalic=0
  44. SilkTextUpright=1
  45. CopperLineWidth=0.2
  46. CopperTextSizeV=1.5
  47. CopperTextSizeH=1.5
  48. CopperTextThickness=0.3
  49. CopperTextItalic=0
  50. CopperTextUpright=1
  51. EdgeCutLineWidth=0.15
  52. CourtyardLineWidth=0.05
  53. OthersLineWidth=0.15
  54. OthersTextSizeV=1
  55. OthersTextSizeH=1
  56. OthersTextSizeThickness=0.15
  57. OthersTextItalic=0
  58. OthersTextUpright=1
  59. SolderMaskClearance=0.051
  60. SolderMaskMinWidth=0.25
  61. SolderPasteClearance=0
  62. SolderPasteRatio=-0
  63. [pcbnew/Layer.F.Cu]
  64. Name=F.Cu
  65. Type=0
  66. Enabled=1
  67. [pcbnew/Layer.In1.Cu]
  68. Name=In1.Cu
  69. Type=0
  70. Enabled=1
  71. [pcbnew/Layer.In2.Cu]
  72. Name=In2.Cu
  73. Type=0
  74. Enabled=1
  75. [pcbnew/Layer.In3.Cu]
  76. Name=In3.Cu
  77. Type=0
  78. Enabled=0
  79. [pcbnew/Layer.In4.Cu]
  80. Name=In4.Cu
  81. Type=0
  82. Enabled=0
  83. [pcbnew/Layer.In5.Cu]
  84. Name=In5.Cu
  85. Type=0
  86. Enabled=0
  87. [pcbnew/Layer.In6.Cu]
  88. Name=In6.Cu
  89. Type=0
  90. Enabled=0
  91. [pcbnew/Layer.In7.Cu]
  92. Name=In7.Cu
  93. Type=0
  94. Enabled=0
  95. [pcbnew/Layer.In8.Cu]
  96. Name=In8.Cu
  97. Type=0
  98. Enabled=0
  99. [pcbnew/Layer.In9.Cu]
  100. Name=In9.Cu
  101. Type=0
  102. Enabled=0
  103. [pcbnew/Layer.In10.Cu]
  104. Name=In10.Cu
  105. Type=0
  106. Enabled=0
  107. [pcbnew/Layer.In11.Cu]
  108. Name=In11.Cu
  109. Type=0
  110. Enabled=0
  111. [pcbnew/Layer.In12.Cu]
  112. Name=In12.Cu
  113. Type=0
  114. Enabled=0
  115. [pcbnew/Layer.In13.Cu]
  116. Name=In13.Cu
  117. Type=0
  118. Enabled=0
  119. [pcbnew/Layer.In14.Cu]
  120. Name=In14.Cu
  121. Type=0
  122. Enabled=0
  123. [pcbnew/Layer.In15.Cu]
  124. Name=In15.Cu
  125. Type=0
  126. Enabled=0
  127. [pcbnew/Layer.In16.Cu]
  128. Name=In16.Cu
  129. Type=0
  130. Enabled=0
  131. [pcbnew/Layer.In17.Cu]
  132. Name=In17.Cu
  133. Type=0
  134. Enabled=0
  135. [pcbnew/Layer.In18.Cu]
  136. Name=In18.Cu
  137. Type=0
  138. Enabled=0
  139. [pcbnew/Layer.In19.Cu]
  140. Name=In19.Cu
  141. Type=0
  142. Enabled=0
  143. [pcbnew/Layer.In20.Cu]
  144. Name=In20.Cu
  145. Type=0
  146. Enabled=0
  147. [pcbnew/Layer.In21.Cu]
  148. Name=In21.Cu
  149. Type=0
  150. Enabled=0
  151. [pcbnew/Layer.In22.Cu]
  152. Name=In22.Cu
  153. Type=0
  154. Enabled=0
  155. [pcbnew/Layer.In23.Cu]
  156. Name=In23.Cu
  157. Type=0
  158. Enabled=0
  159. [pcbnew/Layer.In24.Cu]
  160. Name=In24.Cu
  161. Type=0
  162. Enabled=0
  163. [pcbnew/Layer.In25.Cu]
  164. Name=In25.Cu
  165. Type=0
  166. Enabled=0
  167. [pcbnew/Layer.In26.Cu]
  168. Name=In26.Cu
  169. Type=0
  170. Enabled=0
  171. [pcbnew/Layer.In27.Cu]
  172. Name=In27.Cu
  173. Type=0
  174. Enabled=0
  175. [pcbnew/Layer.In28.Cu]
  176. Name=In28.Cu
  177. Type=0
  178. Enabled=0
  179. [pcbnew/Layer.In29.Cu]
  180. Name=In29.Cu
  181. Type=0
  182. Enabled=0
  183. [pcbnew/Layer.In30.Cu]
  184. Name=In30.Cu
  185. Type=0
  186. Enabled=0
  187. [pcbnew/Layer.B.Cu]
  188. Name=B.Cu
  189. Type=0
  190. Enabled=1
  191. [pcbnew/Layer.B.Adhes]
  192. Enabled=1
  193. [pcbnew/Layer.F.Adhes]
  194. Enabled=1
  195. [pcbnew/Layer.B.Paste]
  196. Enabled=1
  197. [pcbnew/Layer.F.Paste]
  198. Enabled=1
  199. [pcbnew/Layer.B.SilkS]
  200. Enabled=1
  201. [pcbnew/Layer.F.SilkS]
  202. Enabled=1
  203. [pcbnew/Layer.B.Mask]
  204. Enabled=1
  205. [pcbnew/Layer.F.Mask]
  206. Enabled=1
  207. [pcbnew/Layer.Dwgs.User]
  208. Enabled=1
  209. [pcbnew/Layer.Cmts.User]
  210. Enabled=1
  211. [pcbnew/Layer.Eco1.User]
  212. Enabled=1
  213. [pcbnew/Layer.Eco2.User]
  214. Enabled=1
  215. [pcbnew/Layer.Edge.Cuts]
  216. Enabled=1
  217. [pcbnew/Layer.Margin]
  218. Enabled=1
  219. [pcbnew/Layer.B.CrtYd]
  220. Enabled=1
  221. [pcbnew/Layer.F.CrtYd]
  222. Enabled=1
  223. [pcbnew/Layer.B.Fab]
  224. Enabled=1
  225. [pcbnew/Layer.F.Fab]
  226. Enabled=1
  227. [pcbnew/Layer.Rescue]
  228. Enabled=0
  229. [pcbnew/Netclasses]
  230. [pcbnew/Netclasses/Default]
  231. Name=Default
  232. Clearance=0.127
  233. TrackWidth=0.2032
  234. ViaDiameter=0.5
  235. ViaDrill=0.3
  236. uViaDiameter=0.6
  237. uViaDrill=0.1
  238. dPairWidth=0.14732
  239. dPairGap=0.1778
  240. dPairViaGap=0.25
  241. [pcbnew/Netclasses/1]
  242. Name=Microstrip
  243. Clearance=0.127
  244. TrackWidth=0.14732
  245. ViaDiameter=0.5
  246. ViaDrill=0.3
  247. uViaDiameter=0.6
  248. uViaDrill=0.1
  249. dPairWidth=0.14732
  250. dPairGap=0.1778
  251. dPairViaGap=0.25
  252. [schematic_editor]
  253. version=1
  254. PageLayoutDescrFile=
  255. PlotDirectoryName=schematics/
  256. SubpartIdSeparator=0
  257. SubpartFirstId=65
  258. NetFmtName=Pcbnew
  259. SpiceAjustPassiveValues=0
  260. LabSize=157
  261. ERC_TestSimilarLabels=1